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CSU22022, 15th Lecture, Dr. M. Manzke, Page: 1
Multiple-Cycle
Microprogrammed Computer
(32+1) x 32
Register
file
TB || SBTA || SA
TD || DR
(2^32) x 32
Memory
M
PC
RW
PI
PL
IR
Opcode |DR|SA|SB
1
1 + 5
1 + 5 1 + 5
CAR
5 5 5
MUX C
0 1
MUX S
7 6 5 4 3 2 1 0
Z C N Z V C 1 0
MS
3 17
MUX M
0 1
32
MC
1
17
Control Memory
(2^17) x 42
17
Function
Unit
17
IL
32
MUX D
0 1N
A
3
M
S
1
1
M
C
1
I
L
1
P
I
1
P
L
1
T
D
1
T
A
1
T
B
1
M
B
5
F
S
1
MM
1
FS
5
MD
1
MUX B
1 0
32
MB
1
32
A B
Data Out
Data In AddressB
F
Zero Fill
32
MW
32
Bus A
Bus D
1
D
1
V
1
C
1
N
1
Z
V
–
C
–
N
–
Z
2
Bus B
4
Extend 10
A
DR SA
32
1
1
Data Instructions
Data Address
32
Instruction Address
SB
1
M
D
1
R
W
1
M
M
1
M
W
1
R
V
1
R
C
1
R
N
1
R
Z
Sequence Control Datapath Control
Next Address
RV || RC || RN || RZ
Reset
4
4
1
F
L
FL
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 2
Project 2
Microcoded Instruction Set Processor
Project 2 in incremental steps
modifications are required:
Increase the number of registers in the register-file
from 32 to 33
This requires an additional select bit for the two
multiplexers (Bus A and Bus B) and the destination
decoder. These are separate signals (TD, TA, TB) that
are provided by the Control Memory
The size of the registers in the register-file has to be
32 bit (size of instructions)
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 3
Datapath Modifications
Consequently, all components of the Datapath:
MUXs in the Register file
Decoder in the Register file
Arithmetic/logic Unit
Shifter and MUXs …
are 32 bit
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 4
Datapath Modifications
Add and test:
Memory M (512 x 32)
Control Memory (256 x 42)
to your project.
MUX M will feed 32 bit addresses from ether the Bus A
or the PC into the Memory M entity but only the 9 least
significant address bits will be used to index into the
array. This restricts the memory size to 512.
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 5
Control Memory 256 x 42
library IEEE
—
— michael. .ie
— 3rd December 2020
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Next Address MS FS
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
M
C
I
L
P
I
P
L
1
9
1
8
1
7
1
6
1
5
T
D
T
A
T
B
M
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6
M
D
R
W
M
M
M
W
5 4 3 2 1 0
R
V
R
C
R
N
R
Z
F
L
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 6
entity control_memory is
Port (FL : out std_logic; — 0
RZ : out std_logic; — 1
RN : out std_logic; — 2
RC : out std_logic; — 3
RV : out std_logic; — 4
MW : out std_logic; — 5
MM : out std_logic; — 6
RW : out std_logic; — 7
MD : out std_logic; — 8
FS : out std_logic_vector(4 downto 0); — 9 to 13
MB : out std_logic; — 14
TB : out std_logic; — 15
TA : out std_logic; — 16
TD : out std_logic; — 17
PL : out std_logic; — 18
PI : out std_logic; — 19
IL : out std_logic; — 20
MC : out std_logic; — 21
MS : out std_logic_vector(2 downto 0); — 22 to 24
NA : out std_logic_vector(16 downto 0); — 25 to 41
IN_CAR : in std_logic_vector(16 downto 0));
end control_memory;
Next Address MS FS
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
M
C
I
L
P
I
P
L
1
9
1
8
1
7
1
6
1
5
T
D
T
A
T
B
M
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6
M
D
R
W
M
M
M
W
5 4 3 2 1 0
R
V
R
C
R
N
R
Z
F
L
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 7
architecture Behavioral of control_memory is
type mem_array is array(0 to 255) of std_logic_vector(41 downto 0);
begin
memory_m: process(IN_CAR)
variable control_mem : mem_array:=(
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0|
— | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F|
— | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 00
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 01
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 02
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 03
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 04
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 05
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 06
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 07
Next Address MS FS
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
M
C
I
L
P
I
P
L
1
9
1
8
1
7
1
6
1
5
T
D
T
A
T
B
M
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6
M
D
R
W
M
M
M
W
5 4 3 2 1 0
R
V
R
C
R
N
R
Z
F
L
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 8
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0|
— | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F|
— | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 08
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 09
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 0A
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 0B
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 0C
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 0D
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 0E
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 0F
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0|
— | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F|
— | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 10
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 11
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 12
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 13
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 14
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 15
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 16
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– 17
— Address $08 to $17
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 9
— Address $F8 to $FF
•
•
•
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0|
— | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F|
— | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– F8
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– F9
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– FA
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– FB
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– FC
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– FD
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– FE
“00000000000000000 000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0″,– FF
);
variable addr : integer;
variable control_out : std_logic_vector(41 downto 0);
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 10
Begin (process) LSB
begin
addr := conv_integer(IN_CAR);
control_out := control_mem(addr);
FL <= control_out(0);
RZ <= control_out(1);
RN <= control_out(2);
RC <= control_out(3);
RV <= control_out(4);
MW <= control_out(5);
MM <= control_out(6);
RW <= control_out(7);
MD <= control_out(8);
FS <= control_out(13 downto 9);
MB <= control_out(14);
Next Address MS FS
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
M
C
I
L
P
I
P
L
1
9
1
8
1
7
1
6
1
5
T
D
T
A
T
B
M
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6
M
D
R
W
M
M
M
W
5 4 3 2 1 0
R
V
R
C
R
N
R
Z
F
L
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 11
Begin (process) MSB
TB <= control_out(15);
TA <= control_out(16);
TD <= control_out(12);
PL <= control_out(17);
PI <= control_out(19);
IL <= control_out(20);
MC <= control_out(21);
MS <= control_out(24 downto 22);
NA <= control_out(41 downto 25);
end process;
end Behavioral;
Next Address MS FS
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
M
C
I
L
P
I
P
L
1
9
1
8
1
7
1
6
1
5
T
D
T
A
T
B
M
B
1
4
1
3
1
2
1
1
1
0
9 8 7 6
M
D
R
W
M
M
M
W
5 4 3 2 1 0
R
V
R
C
R
N
R
Z
F
L
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 12
VHDL top-level models
The Modified register-file
The Functional Unit
The two memories
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 13
Block Diagram
(32+1) x 32
Register
file
TB || SBTA || SA
TD || DR
(2^32) x 32
Memory
M
PC
RW
PI
PL
IR
Opcode |DR|SA|SB
1
1 + 5
1 + 5 1 + 5
CAR
5 5 5
MUX C
0 1
MUX S
7 6 5 4 3 2 1 0
Z C N Z V C 1 0
MS
3 17
MUX M
0 1
32
MC
1
17
Control Memory
(2^17) x 42
17
Function
Unit
17
IL
32
MUX D
0 1N
A
3
M
S
1
1
M
C
1
I
L
1
P
I
1
P
L
1
T
D
1
T
A
1
T
B
1
M
B
5
F
S
1
MM
1
FS
5
MD
1
MUX B
1 0
32
MB
1
32
A B
Data Out
Data In AddressB
F
Zero Fill
32
MW
32
Bus A
Bus D
1
D
1
V
1
C
1
N
1
Z
V
-
C
-
N
-
Z
2
Bus B
4
Extend 10
A
DR SA
32
1
1
Data Instructions
Data Address
32
Instruction Address
SB
1
M
D
1
R
W
1
M
M
1
M
W
1
R
V
1
R
C
1
R
N
1
R
Z
Sequence Control Datapath Control
Next Address
RV || RC || RN || RZ
Reset
4
4
1
F
L
FL