Use Logisim Evolution v3.7.2.
Task: Cube Root Computer
The goal in this task is to design a synchronous positive-clock-edge triggered sequential system that takes in a 2’s complement number 𝐷𝐼𝑁[23: 0] as input and returns as a 2’s complement number 𝐷𝑂𝑈𝑇[8: 0] the real-valued cube-root of 𝐷𝐼𝑁[23: 0] rounded towards zero.
You can think of your system as a server computer that is responding to requests from an external client as in the figure below (note that the figure omits the clock and reset signals).
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The client interacts with the cube-root server via a four-phase request-acknowledge handshake which involves a signal called 𝑅𝐸𝑄 that goes from client to server, and a signal called 𝐴𝐶𝐾 that goes back from the server to the client. Normally 𝑅𝐸𝑄 and 𝐴𝐶𝐾 are both 0. To initiate a new transaction with the server, the client will put the necessary inputs for the server on 𝐷𝐼𝑁 and set 𝑅𝐸𝑄 = 1, The server, upon seeing 𝑅𝐸𝑄 = 1will know that there is a new task, and start computing using the values on 𝐷𝐼𝑁. When done, it will put the results on 𝐷𝑂𝑈𝑇 and also set 𝐴𝐶𝐾 = 1. The client upon seeing 𝐴𝐶𝐾 = 1 will know that the server is done, and read 𝐷𝑂𝑈𝑇 , and then set 𝑅𝐸𝑄 = 0 to tell server that it is finished reading 𝐷𝑂𝑈𝑇 and the server acknowledges by setting 𝐴𝐶𝐾 = 0. Clearly, client must keep 𝐷𝐼𝑁 stable while 𝑅𝐸𝑄 = 1 and the server must keep 𝐷𝑂𝑈𝑇 stable while 𝐴𝐶𝐾 = 1. The figure below details this handshake (in the figure one an consider 𝑓( ) to represent the computation of the real-value cube root).
Four-Phase Handshake (Return-to-Zero Handshake)
The following pseudo code describes the handshake from the perspective of your system:
InitialState: REQandACKareboth0afterreset
E.g. an input of 419430310 = 0011111111111111111111112 will result in an answer of
16110 = 0101000012, and an input of − 419430310 = 1100000000000000000000012 will result in an answer of − 16110 = 1010111112 .
DOUT[8:0] ACK
Cube-root Server
While True:
Wait for REQ==1
DOUT = RealCubeRoot(DIN) Set ACK=1
Wait for REQ==0
// wait for new DIN
// this may take variable # of clock cycles
// tell client that DOUT is ready
// wait for client to acknowledge reading DOUT // tell client that we are ready for next input
Your design should follow the following specification. You would likely find it useful to consider splitting the task into a controller FSM and a datapath.
Starter Logisim File: final.circ Main Circuit: DUT
𝑅𝑆𝑇, 𝑅𝐸𝑄, 𝐷𝐼𝑁[23: 0] 𝐴𝐶𝐾, 𝐷𝑂𝑈𝑇[8: 0]
Allowed Logisim Modules
● From Gates library: only NOT, and NAND.
● From Memory: only D Flip-Flops and Register from Memory
● From Arithmetic: at most 2 Multipliers, at most 4 Adders, at most 2 Subtractors, at most 2
Comparators. No other components from Arithmetic.
● From Plexers: at most four Multiplexers. No other components from Plexers.
● From wiring: any except Transistor, Pull Resistor, POR, Transmission Gate, Power, and Ground.
○ Note that while you can use Pin in any subcircuits that you define, you must not add any Pin to DUT as that will cause failure with the Autograder.
● From Input/Output: Any.
● None from any other library.
Restrictions
● At most 1000 components total (your design will have a lot fewer; this is just a conservative limit and designed to prevent students who seek to game things by using excessive combinational logic). Logisim components such as pins, tunnels, wires, probes, splitters, LEDs, buttons, etc. that are used for wiring and I/O are excluded. The intent of the problem is that you should not attempt to build complex datapath blocks using simple gates. Please do not attempt to bypass this spirit of the problem.
● Since the system is required to be synchronous, you should not use any asynchronous inputs in any sequential elements that you use – e.g. do not use the asynchronous set or reset signals on flip-flops.
Cost of Logisim Components
● 𝑤-bitwidth NOT: 2 × 𝑤
● 𝑤-bitwidth NAND with 𝑛 inputs: 2 × 𝑤 × 𝑛
● D Flip-Flop: 18
● 𝑤-bitwidth Register: 20 × 𝑤
● 𝑤-bitwidth Adder, Subtractor, Comparator: 28 × 𝑤
● 𝑤-bitwidth Multiplier: 28 × 𝑤!
● 𝑤-bitwidth2″ -to-1Multiplexer:6 ×𝑤×2″ + 2″ + (𝑠>1?2 ×𝑠×2″ ∶ 0)
○ For a 𝑤-bitwidth 2-to-1 Multiplexer, the cost expression simplifies to 12𝑤 + 2.
Desired Behavior:
1. The active edge of 𝐶𝐿𝐾 is the rising edge unless otherwise specified.
2. 𝑅𝑆𝑇 is meant to be used as a synchronous reset signal. Whenever the external world wants to
reset the system, it will assert 𝑅𝑆𝑇 = 1 for at least one rising edge of 𝐶𝐿𝐾 and then make 𝑅𝑆𝑇 = 0 to start normal operation. Note that reset may occur multiple times as the system runs, and even in the middle of a handshake.
3. The external world does not care about the values of output signals on clock edges before the first clock edge after the start at which your system sees 𝑅𝑆𝑇 = 1.
4. If 𝑅𝑆𝑇 = 1 at a clock edge, then the client must see 𝐴𝐶𝐾 = 0 at the next clock edge and likewise your system is assured to see 𝑅𝐸𝑄 = 0 at that clock edge (i.e. the next clock edge).
5. Your system should produce 𝐴𝐶𝐾 and 𝐷𝑂𝑈𝑇 in accordance with the functionality described earlier.
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