Communications
Profs. Leod & ECE3375, Winter 2022
The basics of microcontroller serial communications are discussed. There are a lot of different protocols for communications, and most of them are too complicated to be discussed at this level, but universal asynchronous receiver-transmitters (UART) and the inter-integrated circuit protocol (I2C) are simple enough to be discussed in some detail.
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Communications
Outside of toys, or teaching gimmicks, there are few uses for micro- controllers that do not involve some form of communication with other systems.
Definition: In the context of this course, communication refers to the exchange of information between two otherwise independent CPU-based systems.
It is the independence of the systems that makes communications challenging.
• The CPU exchanges information between peripherals and memory chips, but this is usually in the form of the CPU giv- ing orders, and the other components listening attentively for those orders.
• When attempting to exchange information between two inde- pendent systems, it is quite likely that both CPUs have other things to do than to just wait for the information, and it is also possible that both CPUs may decide to send information (or talk) simultaneously on the same channel.
To address these challenges, computer systems communicate using well-defined protocols. The most common ones used today (USB, Bluetooth, WiFi, etc.) are all too complicated, so we will ignore them for now.
Serial Communications and Shift Registers
From a hardware perspective, the simplest communication method is serial, using a single wire to transmit one bit of information at
a time. The basic hardware element for serial communication is a shift register. A simplified 4-bit shift register is shown in Figure 1, a more practical 8-, 16-, or 32-bit shift register can be constructed by extending the pattern of flip flops. An appropriately-designed shift register can act as a serial receiver and a serial transmitter, with the functionality controlled by software.
• On each clock cycle the contents of each flip flop are shifted to the flip flop immediately on the right.
• New data from serial in can be read in to the left-most flip flop, synchronized by the clock.
• Data is transmitted from the right-most flip flop onto serial out, synchronized by the clock.
• A block of data can also be loaded in parallel to the flip flops from the data bus.
• Subsequently, this data will be sent bit-by-bit to the serial out port, synchronized with the clock.
• A block of data can also be read in parallel from the flip flops to the data bus.
Serial Out
If the serial out port of an n-bit shift register is connected to the se- rial in port of another n-bit shift register, then an n-bit block of data, loaded in parallel into the first shift register will by transmitted to the second shift register in n clock cycles. An example of sending a 4-bit number in this manner is shown in Figure 2.
• A 4-bit number 0b1011 is loaded into the first register from the data bus, synchronously with the clock.
• This number is shifted right bit-by-bit, as each successive LSb is transferred to the second shift register (appearing as the MSb there).
• When the transfer is complete, the result can be read from the second shift register by the data bus.
Figure 1: A simplified 4-bit shift register with parallel load and read.
Serial Data
Serial Data
Serial Data
Serial Data
Serial Data
Serial Data
Figure 2: A schematic representation of trans- mitting a 4-bit value using shift registers. Each “row” in this diagram represents a subsequent
clock cycle.
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
D[3..0] Q[3..0] S in S out
In terms of hardware, Figure 1 is basically a functional communi- cations device. The challenge now lies in software, as is indicated by the process of transmitting a 4-bit number, described above in Figure 2. Namely:
• How does the second microcontroller know when first micro- controller wants to send data?
• How does the second microcontroller know when the first microcontroller is finished sending data?
• How does the second microcontroller know the clock speed of the first microcontroller?
Both microcontrollers need to agree on a set of standards for serial communication in order for one to receive the same information that the other transmitted.
Definition: A communications protocol is a set of standards that describe how information is transmitted.
The communications protocol needs to have the answers to the above questions. Furthermore, for some communication networks, the protocol needs to guide out how conflicts are resolved if two or more systems try to transmit at the same time.
Universal Asynchronous Receiver-Transmitters
Universal asynchronous receiver-transmitters (UARTs) are the hardware components that handle a particular form of serial com- munication. Technically, the actual communication protocol has
a different name, like “RS-232” or “RS-485”. But almost everyone uses UART as the general descriptor for both hardware and soft- ware protocols, so we’ll stick with that. In this protocol the baud rate and communication frame need to be pre-determined.
Definition: The baud rate is the number of pulses transmitted per second. The baud rate is not exactly the same as the “bit rate” of infor- mation transfer, as not all communication pulses correspond to bits of data.
Definition: The communication frame is the set of transmission pulses the comprise the minimal transmission packet.
Definition: A pulse is holding the transmission line at a high or low volt- age for a length of time determined by the baud rate.
Baud rates are always multiples of 300; 9600 is a popular choice. This is one of those bizarre historical artefacts that are held to en- sure backwards-compatibility with archaic equipment that basically no longer exists. 1 A communication frame consists of the follow- ing pulses: 2
• Before sending data, the UART transmission line is idle at a high voltage.
1 In this case, a teletypewriter from the 1960s!
2 I am deliberately reserving the word “bit” for pulses that correspond to data transmission. A lot of other texts and written documentation do not do this, so maybe I am just looking for trouble…
• The start signal is always a single, low voltage pulse.
• The next n pulses transmit bits of data. n is usually 7, 8, or 9. The value of n must be agreed upon by all systems in the communications network. The data can be sent LSb-to-MSb, or MSb-to-LSb.
• A parity pulse (or “parity bit”) for error-checking may come next.
• Finally, the line is held at a high voltage for m pulses as the stop signal. Usually m = 1, but sometimes it may be different.
The receiver must always receive a stop signal for each frame, other- wise it will discard the result as corrupted junk. A stop signal must therefore be sent even if the transmitter will continue to immedi- ately send more information.
The parity bit is another form of error checking. The communica- tions protocol may define data transmission as even or odd parity.
• Before sending the frame, the transmitter will sum the n bits of data. The result will be either an even or an odd number.
• The parity bit will then be set to make sum of the entire n+1 bit sequence even or odd, as agreed upon by the communications protocol.
• After receiving the frame, the receiving system sums the n bits of data and the parity bit, and checks the result against the even or odd protocol. This helps inform the receiver whether the transmission was corrupted.
Start Data
b3 b4b5b6b7 p x Parity
Figure 3: A UART communications frame for transmitting 8 bits of data, with one parity and one stop bit.
Of course, a parity check will only detect single (or triple, or quin- tuple, etc.) pulse transmission errors. A double (or quadruple, or hextuple) pulse transmission error will fool the system into think- ing the data was correctly transmitted.
Example: With an even parity check, an 8-bit transmission of 0b11011000 should have a parity bit of zero, and an 8-bit transmission of 0b11011010 should have a parity bit of 1.
Example: The UART protocol implemented by an arbitrary system calls for 8-bit transmissions, an odd parity check, and a single stop pulse. If communications frame of 01101101011 is received (written with the start pulse on the left and the stop pulse
on the right), the receiver will recognize that the data is cor- rupted — omitting the stop pulse, the data has even parity.
Example: The UART protocol implemented by an arbitrary system calls for 8-bit transmissions, an odd parity check, and a single stop pulse. The communications frame 01101101001 is transmit- ted through a noisy channel and the frame 01100101101 is received. As a double error occurred, the receiver does not recognize that the data has been corrupted. This is one of the limitations with UART.
UART communications frames are abbreviated as n-P -m, where n is the number of bits of data transmitted, P is the parity (0 for even, 1 for odd, or N if there is no parity check), and m is the number
of stop pulses. For low-noise transmission lines, a 8-N-1 frame is popular.
Because the transmitter and receiver have independent clocks, there is no guarantee that these clocks will be synchronized — in fact, it is very likely that they are not.
• Even if the communications medium can support very high baud rates, the baud rate used for communications should still be significantly slower than the clock speed for the trans- mitter and receiver.
• When a start pulse is detected by a receiver, sophisticated receivers will start sampling the communications channel at a higher frequency than the baud rate (often by a factor of ×8 or ×16).
• These oversampled data are averaged by the baud rate. This allows correcting for clock mismatch, and will also smooth out high-frequency noise.
• In a simpler system communications system, the receiver may merely wait for half a pulse-length before sampling.
• This attempts to sample each pulse in the middle, allowing a relatively large clock mismatch to be accommodated without introducing errors in the data.
UART is pretty great, with only one flaw: it is not that great.
• UART doesn’t have a fool-proof method for preventing multi- ple systems from trying to transmit at the same time. Because of the communications frame width and the stop pulses, each
Transmitter:
Parity Stop
Parity Stop
Figure 4: A receiver attempting to read transmit- ted pulses at an interval that is offset by half the pulse width. Although the baud rate is known to both the receiver and transmitter, in this case, the receiver’s clock is slightly faster than the transmitter’s clock. However by attempting to read the middle of each pulse, the data is still transmitted correctly. Here transfer is shown starting with the LSb and proceeding to the
system knows when a transmitter has finished sending a data packet, but that does not provide a mechanism for deciding
which system gets to “talk” next. MSb.
• The worst-case scenario is if two systems try to transmit at ex- actly the same time — this will lead to each system competing to try and drive the channel to high or low voltage, creating a short circuit.
UART works best as a full-duplex communication protocol, where separate transmission/receiving channels are used by each device (see Figure 5). UART also works best when the communication net- work is limited to two systems: a two-system full duplex connection allows both systems to transmit and receive simultaneously.
• The second system is sometimes a hub that uses a different communication standard to communicate with a broader network.
• This is how dial-up internet works — the computer communi- cates with a modem using UART, while the modem converts information to/from an analog signal from the wired phone network.
Figure 5: Half-duplex (top) and full-duplex (bot- tom) UART connections. The half-duplex chan- nel must be pulled up to high voltage externally, and a short circuit will occur if both devices try to transmit at once.
The DE10-Standard has a bunch of UART interfaces, as does the DE1-SoC on the simulator. One of these is of particular note be- cause that provides a good demonstration using the simulator, as discussed at the end of this lesson note.
Inter-Integrated Circuit Protocol
The inter-integrated circuit protocol (I2C or I2C) is a relatively sim- ple communications protocol that addresses some of the problems with UART.
• I2C still uses serial communication over a single-bit data chan- nel (called SDA).
• I2C also sends a common clock signal over a second channel (called SCL).
• I2C allows any number of devices to be connected to these channels.
• I2C operates in “master-slave” mode: one system in the net- work is designated as the master, all other systems are slaves. The master controls which system gets to send or receive data.
• The role of master can be transferred between systems.
The key to the I2C protocol is that clock is not always “ticking”: rather the master starts the clock to activate communication, and stops the clock when communication is completed. In this man- ner, the “start” and “stop” signals are clearly distinct from “data” signals: 3
• Like UART, the data channel SDA is idles at a high voltage. The clock channel SCL also idles high.
3 Unlike UART, where the start and stop pulses were only distinguished by their location in
the communications frame. Any system that somehow misses a start or stop pulse in UART is unable to determine the state of the frame.
Figure 6: A byte of data transmitted by I2C from MSb to LSb. The master only starts the clock (SCL) after the start signal, and stops the clock after the stop signal. After the acknowledge- ment pulse (ACK), any extra clocked pulses are ignored.
b0 Ack Stop Ignored
• A falling edge in SDA when SCL is high indicates the start signal.
• A rising edge in SDA when SCL is high indicates the stop signal.
• Data is otherwise transmitted on rising edges in SCL.
Data in I2C is generally transmitted in bytes, and an acknowledge-
ment from the receiver is expected after each transmission.
• After sending 8 bits, the transmitting system idles for the 9th clock cycle.
• The receiving system is then expected to transmit a single bit of 0 to acknowledge that data was received. If SDA remains high, this indicates the receiving system did not receive the data.
• Another byte of data and an acknowledgement can then be sent, either resending the original information if reception was not acknowledged, or sending the next byte of data.
• If the stop signal is received before 9 clock cycles are com- pleted, any excess pulses are discarded.
This transfer is shown in Figure 6.
As I2C can involve several systems all using the same channels, it is organized similar to a microcontroller.
• Each system has a pre-defined address.
• The master sends the start signal and starts the clock, all the
slave systems prepare to receive data.
• The master then transmits the address of a slave system and an instruction on whether that slave should transmit or re- ceive data (either with the master or another specified slave).
• The data is then transmitted according to the master’s instruc- tions, after which the master sends the stop signal and stops the clock.
If the communications network consists of one microcontroller and several “dumber” devices (perhaps devices that primarily only receive data, like displays or printers; or devices that primarily only transmit data, like sensors or input devices) then the above describes a complete communications network. If the communica- tions network has multiple microcontrollers, then often the master
can send the instructions for one of the slaves to take control of the clock, thus passing the role of master to another device.
• As long as there is only one master, all of the slaves follow instructions, and each device has a unique address, then mul- tiple systems trying to transmit data simultaneously should never occur.
Like UART, almost every microcontroller has the capability for I2C communications. Again, communicating with I2C is a simple matter of looking up the structure of the I2C controller and read- ing/writing data to that peripheral. The DE10-Standard develop- ment board has four I2C controllers, and various peripherals are connected to them.
• One of these is an digital accelerometer, which I intend to demonstrate in a video (I am too lazy to bring the hardware to class).
• Unfortunately I don’t know of any useful I2C device that is implemented on the simulator.
The basic interface for the I2C controllers on the DE10-Standard is discussed at the end of this lesson note.
JTAG UART on the DE10-Standard
Almost every microcontroller has the capability for UART com- munications. Using these communications systems is as simple as interacting with any other memory-mapped peripheral: simply write or read data to the relevant control registers.
• The DE10-Standard has two UART controllers at addresses 0xFFC02000 and 0xFFC03000. These allow full customization of the baud rate and communications frame.
• The baud rate can be configured by writing the appropriate bits to a control register. Baud rates up to 6.25 MBaud are sup- ported.
• The communications frame can be configured, again by writ- ing the appropriate bits to a control register.
• Local storage of 128 B is provided as a first-in, first-out queue for receiving and transmitting data.
The UART controllers have more than 20 control, status, and data registers for various purposes, which I am too lazy to explain here. Instead I will focus on the JTAG UART system, as it clearly demon- strates the functionality of UART but has a much simpler interface.
Example: The DE10-Standard has a JTAG UART 4 that is also imple- mented in the simulator. This peripheral is for communicating with a computer system. In the simulator, ASCII characters
4 JTAG stands for “joint test action group”, which is a protocol for testing and debugging microcontroller systems.
can be written or read from the JTAG window; in hardware a terminal window in the Intel Monitor Program is used for the same purpose. The JTAG UART is memory-mapped to
Read Interrupt Pending Write Interrupt Pending Free space for writing Accessed
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0
Free space for reading Ready Data
address 0xff201000, and has the structure shown in Figure 7. The baud rate and communications frame are predefined, which greatly simplifies using this peripheral. 5 In the sim- plest method of operating, data is written or read to the data register. For reading data, bit 15 of the data register indicates when a frame of data was successfully read by the UART.
The JTAG UART contains on-chip memory, organized as a queue 6 This internal data structure makes transmitting/re- ceiving data from the UART particularly simple.
• To send a reasonably large amount of data we can just continually write to the JTAG UART.
• The JTAG UART will worry about all the details in actu- ally transmitting this data, and will do so in the order
Enable Write Interrupts Enable Read Interrupts
[base]+0x04:Control [base]+0x0
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