Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C (Dr. )
Chapter 15 General-purpose Timers
ECE3375B: Microprocessors and Microcomputers Electrical and Computer Engineering Western University
Dr. Leod (Section 1, Dr. (Section 2,
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Timer Overview
Free-run counter (independent of processor) Functions
Input capture
Output compare
Available timers in DE-10 Computer system Private timer
Watchdog timer
Global timer
HPS timers
Interval timer
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ECE 3375b (A. Reyhani)
Timer Organization and Counting Modes
A timer is a free-run hardware counter that increments or decrements by one for every clock cycle.
The counter runs continuously until the timer is disabled.
The counting process restarts automatically when the counter reaches 0
during down-counting or some maximum value during up-counting.
Auto-Reload Register (ARR)
Reload trigger fCL_CNT
Counter is incremented/decremented once per cycle.
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Timer: Clock
UIF: Update Interrupt Flag UIE: Update Interrupt Enable
Auto-Reload Register (ARR)
Reload trigger
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Frequency:
Counter is incremented/decremented once per cycle.
𝑓 = 𝐶𝐿_𝑃𝑆𝐶
𝐶𝐾_𝐶𝑁𝑇 𝑃𝑆𝐶 + 1
Software can change the prescaler (PSC) to allow the timer clocked at desired rate.
Timer: Clock (Example)
UIF: Update Interrupt Flag UIE: Update Interrupt Enable
Auto-Reload Register (ARR)
Reload trigger
PSC 15,999
Prescaler 1KHzCounter is incremented/decremented once per cycle.
𝑓 = 16𝑀𝐻𝑧 =1𝐾𝐻𝑧
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Timer: Output Compare
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Reload trigger fCL_CNT
Auto-Reload Register (ARR)
Timer Output
Compare & Capture Register (CCR)
Timer: Input Capture
Auto-Reload Register (ARR)
Reload trigger fCL_CNT
Register (CCR)
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Output Compare
If a timer works as output compare
The comparator consistently compares the counter value with some given
constant and generates an output or an interrupt if they are equal.
Software can program the constant value to control the timing of outputs or interrupts.
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Input Capture
Capture the timestamp of the occurrence of a rising or a falling edge transition in a digital signal
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External signal
1) Hardware copies counter to CCR, thus CCR = 63
2) Hardware generates an interrupt to run timer ISR()
1) Hardware copies counter to CCR, thus CCR = 30
2) Hardware generates an interrupt to run timer ISR()
Time span between two events = 63 – 30 = 33 time units
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Input Capture
Record the timestamp of an external event Capture both rising and falling edges
𝑇𝑖𝑚𝑒𝑆𝑝𝑎𝑛=𝑇 −𝑇 21
External Signal 1
External Signal 2
Measuring low or high time
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Input Capture
Capture only rising edges or only falling edges 𝑇𝑖𝑚𝑒𝑆𝑝𝑎𝑛=𝑇 −𝑇
External Signal 1
External Signal 2
Measuring the period
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Input Capture
Latch the counter value into CCR after a transition is detected
If enabled, generate an interrupt to inform the processor to read CCR
Hold in CCR (Capture/Compare register)
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Counter is incremented/decremented once per cycle.
Timer: Upcounting mode, ARR = 6
𝒄𝒐𝒖𝒏𝒕𝒆𝒓 𝒄𝒍𝒐𝒄𝒌 𝒑𝒆𝒓𝒊𝒐𝒅 = 𝟏
Counter 1 2
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
34343434 1 2 1 2 1 2
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Timer Counter
Capture only rising edges
External Input Signal
𝑇𝑖𝑚𝑒 𝑆𝑝𝑎𝑛 = (𝐶𝐶𝑅𝑛𝑒𝑤 − 𝐶𝐶𝑅𝑜𝑙𝑑 ) × 𝑓
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 15
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Timers of DE10-Standard Computer
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Timer Modules of DE10-Standard Computer
The hard processor system (HPS) includes several hardware timer modules that can
be used to keep track of time intervals.
The ARM A9 MPCore includes one private timer module for each A9 core,
The HPS provides four other timer modules that can be used by either A9 core.
The ARM A9 MPCore has a global timer that is shared by both A9 cores, as well as a watchdog timer for each processor.
Also, the HPS has two additional watchdog timers.
The DE10-Standard Computer includes two interval timer modules implemented in
the FPGA that can be used by the ARM A9 processor.
All counters (except the global counter) are 32-bit decrementing counter with auto- decrementing feature
The global timer is a 64-bit incrementing counter with an auto-incrementing feature.
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ARM A9 MPCore Private Timer
Load Register
Bit 1 in Control
Bit 0 in Interupt Status Register
Bit 2 in Control
fPERIPHCLK= 200 MHz
Reload trigger
32-bit down Counter
Prescaler E
Bit 0 in Control
• These registers have the base address 0xFFFEC600
• They can be read or written using word accesses
DE10-STANDARD COMPUTER SYSTEM WITH ARM* CORTEX* A9 ECE 3375b (A. Reyhani)
ARM A9 MPCore Private Timer: Load Register
The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled (A=1).
To use the timer, it is necessary to first write an initial count value into the Load register.
Writing to the Timer Load Register means that you also write to the Timer Counter Register.
Bit 1 in Control
I interrupt
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fPERIPHCLK= 200 MHz
32-bit down Counter
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Load Register
ARM A9 MPCore Private Timer: Counter Register
The Timer Counter Register is a decrementing counter.
The Timer Counter Register decrements if the timer is enabled (E=1) using the
timer enable bit in the Timer Control Register.
The current value of the timer is available to software in the Counter register
fPERIPHCLK= 200 MHz
PSC fCL_CNT AND E
32-bit down Counter event I 20 DE10-STANDARD COMPUTER SYSTEM WITH ARM* CORTEX* A9
AND interrupt
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Bit 0 in Control Register
Load Register
ARM A9 MPCore Private Timer: Counter Register
When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value.
If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops.
When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled (I=1) in the Timer Control Register.
Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value.
Bit 1 in Control
fPERIPHCLK= 200 MHz
PSC fCL_CNT AND E
AND interrupt Bit 2 in Control Register
32-bit down Counter event I
ARM Cortex A9 MPCore Technical Reference Manual ECE 3375b (A. Reyhani)
Load Register
ARM A9 MPCore Private Timer: Control and Interrupt Status Registers
After writing an initial value into Load register, the timer can then be started by setting the enable bit E in the Control register to 1, and it can be stopped by setting E back to 0.
Once enabled the timer decrements its count value until reaching 0.
Load Register
I interrupt
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fPERIPHCLK= 200 MHz
32-bit down Counter
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ARM A9 MPCore Private Timer: Control and Interrupt Status Registers
When the timer reaches 0:
It sets the F bit in the Interrupt status register.
The F bit can be checked by software using polled-I/O to determine when the timer period has expired. The F bit can be reset to 0 by writing a 1 into it.
If bit I in the Control register is set to 1, then a processor interrupt can be generated
The timer will stop if the auto bit (A) in the control register is set to 0. But if bit A is set to 1, then the timer
will automatically reload the value in the Load register and continue decrementing.
fPERIPHCLK= 200 MHz
PSC fCL_CNT AND E
32-bit down Counter event I 23 DE10-STANDARD COMPUTER SYSTEM WITH ARM* CORTEX* A9
AND interrupt
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Load Register
ARM A9 MPCore Private Timer: Control and Counter Registers
The current value of the timer is available to software in the Counter register
The timer uses a clock frequency of 200 MHz.
The Prescaler field in the Control register can be used to slow down the
counting rate as follows
𝑓 = 200 𝑀𝐻𝑧
fPERIPHCLK= 200 MHz
PSC fCL_CNT AND
32-bit down Counter event I 24 DE10-STANDARD COMPUTER SYSTEM WITH ARM* CORTEX* A9
AND interrupt
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clock Prescaler E
Load Register
Example 1: Private_timer_LED9.s
This program (Private_timer_LED9.s) provides a simple example of code for the ARM A9.
The program performs the following:
starts the ARM A9 private timer
loops forever, toggling the bit 9 red light LEDs when the timer expires
DE10-STANDARD COMPUTER SYSTEM WITH ARM* CORTEX* A9
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Example 1: Private_timer_LED9.s
To use the timer:
Write 200×10^6 into load register for 1 s delay; should have been 200×10^6-1 to be precise (lines16-17)
Write to timer control register (lines 18-19)
Prescaler=0, no interrupt (I=0), auto reload (A=1), enable (E=1)
The F bit is read and checked by software using polled-I/O to determine when the timer period has expired (lines 22-25)
No interrupt is generated as I=0
The F bit is reset to 0 by writing a 1 into it (line
Thecounterwillbereadyforthenextdelaycycle
Turn on/off bit 9 of red LEDs (line 15, line 21)
Toggle the bit 9 red LEDs value by XORing with 1 (line 27)
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Example 2: Private_timer_LED9.c
This C code (Private_timer_LED9.c) performs the same operation as the previous assembly code
The program performs the following:
starts the ARM A9 private timer
loops forever, toggling the bit 9 red light LEDs when the timer expires
Declare volatile pointers to I/O registers (lines 13-14)
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Example 2: Private_timer_LED9.c
To use the timer:
Write 200×10^6 into load register for 1 s delay; should have been 200×10^6-1 to be precise (line 18)
Write to timer control register (line 19)
Prescaler=0, no interrupt (I=0), auto reload (A=1), enable (E=1)
The F bit is read and checked by software using polled-I/O to determine when the timer period has expired (line 23)
No interrupt is generated as I=0
The F bit is reset to 0 by writing a 1 into it (line
Thecounterwillbereadyforthenextdelaycycle
Turn on/off bit 9 of red LEDs (line 17, line 22)
Toggle the bit 9 red LEDs value by XORing with 1 (line 26)
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Example 3: Using the Parallel Ports with Assembly Language-Repeated for reference
The code (rotate2.s) displays the values of the SW switches on the LED lights.
A rotating pattern is displayed on the LEDs
This pattern is rotated to the left by using
an ARM A9 rotate instruction
a delay loop is used to make the shifting slow enough to observe.
In the new code, the private timer is used for one sec delay
The pattern can be changed to the values of the SW switches by pressing a pushbutton KEY.
When a pushbutton key is pressed, the program waits in a loop until the key is released.
DE10-STANDARD COMPUTER SYSTEM WITH ARM* CORTEX* A9
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Example 3: Parallel Ports with Assembly Language using the Private Timer
The code (Rotate_Private_Timer.s) displays the values of the SW switches on the LED lights.
A rotating pattern is displayed on the LEDs
This pattern is rotated to the left by using an ARM
A9 rotate instruction
The pattern can be changed to the values of the SW switches by pressing a pushbutton KEY.
When a pushbutton key is pressed, the program waits in a loop until the key is released.
Call DELAY subroutine for one sec delay (line 44)
The code for DELAY (lines 47-58, line 2) is
obtained from the “Private_timer_LED9.s” code
Since R1 and R3 are used in DELAY, they are pushed (line 43) and popped (line 45) before and after calling the DELAY subroutine (line 44)
Therefore, the SP should be initialized (line 15)
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Example 4: Using the Parallel Ports with C Code-Repeated for reference
It performs the same operation as the previous assembly code
Declare volatile pointers to I/O registers so that the compiler does not perform optimization on the code (lines 14-16)
A for loop is used for delay only without performing anything inside the loop (line 36)
In the new code, the private timer is used for one sec delay
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Example 4: Parallel Ports with C code using the Private Timer
The code (Rotate_Private_timer.c)
performs the same operation as the
previous assembly code displays the
values of the SW switches on the LED lights.
Call private_timer subroutine for one sec delay (line 40)
The code for private_timer (lines 45- 49, line 1, line 23) is obtained from the “Private_timer_LED9.c” code
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About the private timer and watchdog blocks
List of features of the private timer and watchdog blocks.
A 32-bit counter that generates an interrupt when it reaches zero. An eight-bit prescaler value to qualify the clock period.
Configurable single-shot or auto-reload modes.
Configurable starting values for the counter.
The clock for these blocks is PERIPHCLK.
The watchdog can be configured as a timer
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About the private timer and watchdog blocks (cont.)
These registers have the base address 0xFFFEC600
All registers except the Watchdog Disable Register can be read or written (RW) using
word accesses
The Watchdog Disable Register is a written-only (WO) register and is used to switch from watchdog to timer mode.
Offset Type Reset Value
Function/Register name
Private Timer Load Register
Private Timer Counter Register Private Timer Control Register
Private Timer Interrupt Status Register Watchdog Load Register
Watchdog Counter Register Watchdog Control Register Watchdog Interrupt Status Register Watchdog Reset Status Register
Watchdog Disable Register
0x00 RW 0x04 RW 0x08 RW 0x0C RW 0x20 RW 0x24 RW 0x28 RW 0x2C RW 0x30 RW 0x34 WO
0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000
List of timer and watchdog registers.
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What is Watchdog Timer?
“Watchdog Timer” is a peripheral device which consists of a hardware counter that decrements automatically each clock cycle.
When the count of watchdog timer reaches zero, the hardware will automatically reset the Computer System.
For special circumstances that the code hangs and computer systems freezes, the easy way (and sometimes the only way) to solve the problem is to reset the computer
The manual reset is not possible for applications, such as a satellite.
refresh Time out
Watchdog Timer
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What is Watchdog Timer?
The watchdog should be configured and enabled by software.
Once enabled, the system software needs to refresh/restart the counter
periodically to prevent the device/computer from being reset.
This operation is usually referred to as “feeding”, or “kicking” the dog.
If software is unable to restart the watchdog, the system is not running as expected and needs to be reset
Watchdog timers may have either fixed or programmable time intervals
Typically, watchdog time intervals range from ten milliseconds to a minute or more
refresh Time out
Watchdog Timer
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ARM A9 MPCore Watchdog Timer
Each watchdog timer has 6 32-bit registers
The first four registers are similar to the Private Timer The last two registers are new and for the watchdog
0xFFFEC620 0xFFFEC624 0xFFFEC628 0xFFFEC62C 0xFFFEC630 0xFFFEC634
Register name
Load Register Counter Register Control Register
Interrupt Status Register Reset Status Register Disable Register
ARM A9 MPCore Watchdog Timer: Load Register
It performs the same as operation as the Load register of Private counter
The Watchdog Load Register contains the value copied to the Watchdog Counter Register
when it decrements down to zero with auto reload mode enabled in Timer mode.
Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register.
0xFFFEC620
0xFFFEC624 0xFFFEC628 0xFFFEC62C 0xFFFEC630 0xFFFEC634
38 ARM Cortex A9 MPCore Technical Reference Manual
Register name
Load Register
Counter Register Control Register
Interrupt Status Register Reset Status Register Disable Register
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ARM A9 MPCore Watchdog Timer: Counter Register
The Watchdog Counter Register is a down counter.
It decrements if the Watchdog is enabled using the Watchdog
enable bit in the Watchdog Control Register.
When the Watchdog Counter Register reaches zero and auto reload mode is enabled, and in timer mode, it reloads the value in the Watchdog Load Register and then decrements from that value.
If auto reload mode is not enabled or the watchdog is not in timer mode, the Watchdog Counter Register decrements down to zero and stops.
When in watchdog mode, the only way to update the Watchdog Cou
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