Chapter …
The Processor
Copyright By PowCoder代写 加微信 powcoder
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Introduction
CPU performance factors
Instruction count
Determined by ISA and compiler
CPI and Cycle time
Determined by CPU hardware
We will examine two RISC-V implementations
A simplified version
A more realistic pipelined version
Simple subset, shows most aspects
Memory reference: ld, sd
Arithmetic/logical: add, sub, and, or
Control transfer: beq
§4.1 Introduction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Instruction Execution
PC instruction memory, fetch instruction
Register numbers register file, read registers
Depending on instruction class
Use ALU to calculate
Arithmetic result
Memory address for load/store
Branch comparison
Access data memory for load/store
PC target address or PC + 4
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
CPU Overview
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Multiplexers
Can’t just join wires together
Use multiplexers
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Logic Design Basics
§4.2 Logic Design Conventions
Information encoded in binary
Low voltage = 0, High voltage = 1
One wire per bit
Multi-bit data encoded on multi-wire buses
Combinational element
Operate on data
Output is a function of input
State (sequential) elements
Store information
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Combinational Elements
Multiplexer
Y = S ? I1 : I0
Arithmetic/Logic Unit
Y = F(A, B)
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Sequential Elements
Register: stores data in a circuit
Uses a clock signal to determine when to update the stored value
Edge-triggered: update when Clk changes from 0 to 1
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Sequential Elements
Register with write control
Only updates on clock edge when write control input is 1
Used when stored value is required later
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Clocking Methodology
Combinational logic transforms data during clock cycles
Between clock edges
Input from state elements, output to state element
Longest delay determines clock period
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Building a
Elements that process data and addresses
in the CPU
Registers, ALUs, mux’s, memories, …
We will build a RISC-V datapath incrementally
Refining the overview design
§4.3 Building a Datapath
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Instruction Fetch
64-bit register
Increment by 4 for next instruction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
R-Format Instructions
Read two register operands
Perform arithmetic/logical operation
Write register result
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load/Store Instructions
Read register operands
Calculate address using 12-bit offset
Use ALU, but sign-extend offset
Load: Read memory and update register
Store: Write register value to memory
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Branch Instructions
Read register operands
Compare operands
Use ALU, subtract and check Zero output
Calculate target address
Sign-extend displacement
Shift left 1 place (halfword displacement)
Add to PC value
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Branch Instructions
re-routes wires
Sign-bit wire replicated
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Composing the Elements
First-cut data path does an instruction in one clock cycle
Each datapath element can only do one function at a time
Hence, we need separate instruction and data memories
Use multiplexers where alternate data sources are used for different instructions
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
R-Type/Load/Store Datapath
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Full Datapath
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
ALU Control
ALU used for
Load/Store: F = add
Branch: F = subtract
R-type: F depends on opcode
§4.4 A Simple Implementation Scheme
ALU control Function
0110 subtract
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
ALU Control
Assume 2-bit ALUOp derived from opcode
Combinational logic derives ALU control
opcode ALUOp Operation Opcode field ALU function ALU control
ld 00 load register XXXXXXXXXXX add 0010
sd 00 store register XXXXXXXXXXX add 0010
beq 01 branch on equal XXXXXXXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
The Main Control Unit
Control signals derived from instruction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Datapath With Control
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
R-Type Instruction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load Instruction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
BEQ Instruction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Performance Issues
Longest delay determines clock period
Critical path: load instruction
Instruction memory register file ALU data memory register file
Not feasible to vary period for different instructions
Violates design principle
Making the common case fast
We will improve performance by pipelining
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipelining Analogy
Pipelined laundry: overlapping execution
Parallelism improves performance
§4.5 An Overview of Pipelining
Four loads:
= 8/3.5 = 2.3
= 2n/0.5n + 1.5 ≈ 4
= number of stages
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
RISC-V Pipeline
Five stages, one step per stage
IF: Instruction fetch from memory
ID: Instruction decode & register read
EX: Execute operation or calculate address
MEM: Access memory operand
WB: Write result back to register
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Performance
Assume time for stages is
100ps for register read or write
200ps for other stages
Compare pipelined datapath with single-cycle datapath
Instr Instr fetch Register read ALU op Memory access Register write Total time
ld 200ps 100 ps 200ps 200ps 100 ps 800ps
sd 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Performance
Single-cycle (Tc= 800ps)
Pipelined (Tc= 200ps)
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Speedup
If all stages are balanced
i.e., all take the same time
Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
If not balanced, speedup is less
Speedup due to increased throughput
Latency (time for each instruction) does not decrease
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipelining and ISA Design
RISC-V ISA designed for pipelining
All instructions are 32-bits
Easier to fetch and decode in one cycle
c.f. x86: 1- to 17-byte instructions
Few and regular instruction formats
Can decode and read registers in one step
Load/store addressing
Can calculate address in 3rd stage, access memory in 4th stage
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Situations that prevent starting the next instruction in the next cycle
Structure hazards
A required resource is busy
Data hazard
Need to wait for previous instruction to complete its data read/write
Control hazard
Deciding on control action depends on previous instruction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Structure Hazards
Conflict for use of a resource
In RISC-V pipeline with a single memory
Load/store requires data access
Instruction fetch would have to stall for that cycle
Would cause a pipeline “bubble”
Hence, pipelined datapaths require separate instruction/data memories
Or separate instruction/data caches
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Data Hazards
An instruction depends on completion of data access by a previous instruction
add x19, x0, x1
sub x2, x19, x3
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Forwarding (aka Bypassing)
Use result when it is computed
Don’t wait for it to be stored in a register
Requires extra connections in the datapath
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load-Use Data Hazard
Can’t always avoid stalls by forwarding
If value not computed when needed
Can’t forward backward in time!
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Code Scheduling to Avoid Stalls
Reorder code to avoid use of load result in the next instruction
C code for a = b + e; c = b + f;
ld x1, 0(x0)
ld x2, 8(x0)
add x3, x1, x2
sd x3, 24(x0)
ld x4, 16(x0)
add x5, x1, x4
sd x5, 32(x0)
ld x1, 0(x0)
ld x2, 8(x0)
ld x4, 16(x0)
add x3, x1, x2
sd x3, 24(x0)
add x5, x1, x4
sd x5, 32(x0)
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Control Hazards
Branch determines flow of control
Fetching next instruction depends on branch outcome
Pipeline can’t always fetch correct instruction
Still working on ID stage of branch
In RISC-V pipeline
Need to compare registers and compute target early in the pipeline
Add hardware to do it in ID stage
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Stall on Branch
Wait until branch outcome determined before fetching next instruction
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Branch Prediction
Longer pipelines can’t readily determine branch outcome early
Stall penalty becomes unacceptable
Predict outcome of branch
Only stall if prediction is wrong
In RISC-V pipeline
Can predict branches not taken
Fetch instruction after branch, with no delay
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
More-Realistic Branch Prediction
Static branch prediction
Based on typical branch behavior
Example: loop and if-statement branches
Predict backward branches taken
Predict forward branches not taken
Dynamic branch prediction
Hardware measures actual branch behavior
e.g., record recent history of each branch
Assume future behavior will continue the trend
When wrong, stall while re-fetching, and update history
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Summary
Pipelining improves performance by increasing instruction throughput
Executes multiple instructions in parallel
Each instruction has the same latency
Subject to hazards
Structure, data, control
Instruction set design affects complexity of pipeline implementation
The BIG Picture
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
§4.6 and Control
Right-to-left flow leads to hazards
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline registers
Need registers between stages
To hold information produced in previous cycle
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Operation
Cycle-by-cycle flow of instructions through the pipelined datapath
“Single-clock-cycle” pipeline diagram
Shows pipeline usage in a single cycle
Highlight resources used
c.f. “multi-clock-cycle” diagram
Graph of operation over time
We’ll look at “single-clock-cycle” diagrams for load & store
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
IF for Load, Store, …
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
ID for Load, Store, …
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
EX for Load
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
MEM for Load
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
WB for Load
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Corrected Datapath for Load
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
EX for Store
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
MEM for Store
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
WB for Store
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Multi-Cycle Pipeline Diagram
Form showing resource usage
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Multi-Cycle Pipeline Diagram
Traditional form
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Single-Cycle Pipeline Diagram
State of pipeline in a given cycle
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipelined Control (Simplified)
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipelined Control
Control signals derived from instruction
As in single-cycle implementation
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipelined Control
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Data Hazards in ALU Instructions
Consider this sequence:
sub x2, x1,x3
and x12,x2,x5
or x13,x6,x2
add x14,x2,x2
sd x15,100(x2)
We can resolve hazards with forwarding
How do we detect when to forward?
§4.7 Data Hazards: Forwarding vs. Stalling
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Dependencies & Forwarding
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Detecting the Need to Forward
Pass register numbers along pipeline
e.g., ID/EX.RegisterRs1 = register number for Rs1 sitting in ID/EX pipeline register
ALU operand register numbers in EX stage are given by
ID/EX.RegisterRs1, ID/EX.RegisterRs2
Data hazards when
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs1
1b. EX/MEM.RegisterRd = ID/EX.RegisterRs2
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs1
2b. MEM/WB.RegisterRd = ID/EX.RegisterRs2
pipeline reg
pipeline reg
Chapter 4 — The Processor — *
Publishers
Publishers
Chapter 4 — The Processor
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Detecting the Need to Forward
But only if forwarding instruction will write to a register!
EX/MEM.RegWrite, MEM/WB.RegWrite
And only if Rd for that instruction is not x0
EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0
Chapter 4 — The Processor — *
Publishers
Publishers
程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com