LE/EECS 2021
COMPUTER ORGANIZATION
RVS Review*
Data Representations and Assembler Commands
Copyright By PowCoder代写 加微信 powcoder
*See the RVS Assembler Manual
Signed Integers (2’s compl.)
We have a single representation for 0
0:0x0000000000000000 -0:0x0000000000000000
Why? Let’s calculate:
Invert: 0x0000000000000000=>
0xFFFFFFFFFFFFFFFF
Add 1:0xFFFFFFFFFFFFFFFF+1=>
0x(1)0000000000000000
Data Types and Assembler Commands — 2
Signed Integers (2’s compl.)
If we were to have a sign bit and a value: 0:0x0000000000000000
-0:0x8000000000000000
There would be 2 representation for 0.
One would be for +0 and the other one would be for -0, as shown above.
Complications:
How do we check if an obtained result is 0? Do we need to do 2 comparisons?
Data Types and Assembler Commands — 3
Signed Integers (2’s compl.)
-1 is all 1’s -1:0xFFFFFFFFFFFFFFFF Why? Let’s calculate:
1:0x0000000000000001 Invert:0x0000000000000001 =>
0xFFFFFFFFFFFFFFFE
Add 1:0xFFFFFFFFFFFFFFFE+1=> 0xFFFFFFFFFFFFFFFF
-2 is 0xFFFFFFFFFFFFFFFE
(because we added 1 to it and got -1)
Data Types and Assembler Commands — 4
Signed Integers (2’s compl.)
Therefore when we invert the bits of a value v we get the value -v-1.
This works both for positive and for negative values, for example:
Invert: 5 => -5-1=-6 Invert: -6 => 6-1= 5
Data Types and Assembler Commands — 5
Signed Integers (2’s compl.)
What is the largest positive value? (+max):0x7FFFFFFFFFFFFFFF
Its MSB is 0 (because it is positive)
All its other bits are 1’s (to get the max)
What is the smallest negative value? Invert:0x7FFFFFFFFFFFFFFF =>
0x8000000000000000
It is negative (because its MSB is 1) (-max)=-(+max)-1
There is one extra negative value!
Data Types and Assembler Commands — 6
Signed Integers (2’s compl.)
Example with 4-bit signed integers. The largest positive value is:
(+max):0111 (4+2+1=7)
Its MSB is 0 (because it is positive)
All its other bits are 1’s (to get the max)
The smallest negative value is: Invert: 0111=>1000
It is negative (because its MSB is 1) (-max)=-(+max)-1=-7-1=-8
All values:-8,-7,-6,-5,-4,-3,-2,-1,
0,1,2,3,4,5,6,7
Data Types and Assembler Commands — 7
Sign Extensions (2’s compl.)
addi x5,x0, 1 ;0x001
addi x6,x0,-1 ;0xFFF
x5 t0 0x0000000000000001 1 x6 t1 0xFFFFFFFFFFFFFFFF -1
But how to put just 0xFFF in a register?
In RISC-V you cannot do this with one instruction because immediate values are always treated as signed integers.
There is no way in RISC-V to specify that an immediate value is unsigned.
Data Types and Assembler Commands — 8
Sign Extensions (2’s compl.)
Here are the consequences of this ISA decision. Putting 0x1400 in a register is simple:
addi x6,x5,0x400
But putting 0x1800 in a register is not so simple:
lui x5,2 ;we had to add 1 here
addi x6,x5,0x800
The only difference is that the last 3 hex digits of 0x1400 happen to represent a positive 12-bit number while the last 3 hex digits of 0x1800 a negative 12-bit number.
Data Types and Assembler Commands — 9
Sign Extensions (2’s compl.)
Why do we add 1?
Let’s v be the unsigned value of the LSB 11 bits marked below by x:
Positive: 0xxx xxxx xxxx =v
Unsigned: 0xxx xxxx xxxx =v
Negative: 1xxx xxxx xxxx =-211+v Unsigned: 1xxx xxxx xxxx = 211+v
The difference in the negative case is -212 Adding 1 to the constant in lui increases the value by 212 because it is shifted 12 bits to the
Data Types and Assembler Commands — 10
Unsigned Immediates?
Can’t we have an unsigned version of addi e.g. addiu?
Adding unsigned immediates will require unsigned versions for all immediate instructions. More bits in the opcode and/or the func fields will be needed so we may end up with less bits for the immediate values.
Moreover, as immediate values are known at compile time (a clever) compiler can do the necessary adjustments without generating any extra machine instructions.
Data Types and Assembler Commands — 11
32-bit Constants Most constants are small
12-bit immediate is sufficient
For the occasional 32-bit constant
lui rd, constant
Copies 20-bit constant to bits [31:12] of rd
Extends bit 31 to bits [63:32] (treated as signed!) Clears bits [11:0] of rd to 0
lui x19, 976 // 0x003D0
addi x19,x19,128 // 0x500
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0011 1101 0000
0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0011 1101 0000
0101 0000 0000
Data Types and Assembler Commands — 12
addi and lui addi x5, x0, c
Two step process:
At compile time the assembler will store the
immediate constant c into the 12 bits of the
immediate field of the instruction
At execution time the RISC-V architecture will
use the 12 bits from the immediate field interpreting them as a signed integer.
The same two step process but the immediate field is 20 bits.
Data Types and Assembler Commands — 13
Creating Masks (1…1-bits)
;Loading a 12-bit immediate value ;0x00000000000000f0
addix5, x0, 0xf0
;Loading a 20-bit immediate value ;0x000000000fff0000
lui x6, 0xfff0
;Loading and shifting a 20-bit immediate value ;0x0000000000ffff00
lui x7, 0xffff srlix7, x7, 4
;Loading all 1’s, shifting to trim, and shifting to position
;0x0000000fffffff00
addix8, x0, -1 ;load all 1’s
sllix8, x8, 36 ;trim 36 bits
srlix8, x8, 28 ;shift to the right position
Data Types and Assembler Commands — 14
Assembler Commands
v1: EQU 0xfff
v2: EQU -1
SYMBOL TABLE
0x0000000000000fff v1
0xffffffffffffffff v2
v1- no sign extension because assembler commands and operations work with 64-bit
constants.
V2- the 64-bit representation of -1 is used
Data Types and Assembler Commands — 15
Assembler Commands
v2: EQU -1
v3: EQU v2>>1
SYMBOL TABLE 0xffffffffffffffff v2 0x7fffffffffffffff v3
The assembly operations, e.g. shift right (>>) treat the values as unsigned (>> works
as logical shift and not as arithmetic shift). Data Types and Assembler Commands — 16
Assembler Commands
c1: EQU c2:EQU c3: EQU c4: EQU
0xfff ;4095 (an unsigned number that fits in 12 bits)
4095 ;0xfff(an unsigned number that fits in 12 bits)
-1 ;0xFFFFFFFFFFFFFFFF (a very big 64-bit unsigned number)
0xfffff ;(an unsigned number that fits in 20 bits)
x5, x0, c1 ;unsigned 4095 is treated as signed -1
x5, x0, c2 ;unsigned 4095 is treated as signed -1
x5, x0, c3 ;error- the unsigned number does not fit in 12 bits x6, c2 ;(unsigned 4095)*4096=16773120 (12 shifts to the left) x7, c4 ;0xfffffffffffff000 -4096
x8, x7, 32 0xFFFFF00000000000 -17592186044416
x8, x8, 32 ;0x00000000FFFFF000 4294963200
SYMBOL TABLE
0x0000000000000000 START 0x0000000000000fff c1 0x0000000000000fff c2 0xffffffffffffffff c3 0x00000000000fffff c4 INT Regs
x5 t0 0xFFFFFFFFFFFFFFFF -1
x6 t1 0x0000000000fff000 16773120 x7 t2 0xfffffffffffff000 -4096
x8 s0 0x00000000FFFFF000 4294963200
Data Types and Assembler Commands — 17
Assembler Commands
DD 0xfff ;Define Double (word)
0x0000000000000000 0x0000000000000fff 4095
0x0000000000000008 0xffffffffffffffff -1
DD works with 64-bit constants and fills the entire double word of 64 bits.
No sign extension is needed because the size of the constant is equal to the size of the destination.
Data Types and Assembler Commands — 18
Assembler Commands
DW 0xfff ;Define Word DW -1
DW 0xfff, -1
0x0000000000000000 0x0000000000000fff 4095
0x0000000000000008 0x00000000ffffffff 4294967295
0x0000000000000010 0xffffffff00000fff -4294963201
DW works with 32-bit constants and fill the lower 4 bytes of the double word.
DW fills a double word using two constants. Data Types and Assembler Commands — 19
Assembler Commands
DH 0x0f ;Define Half (word) DH -1
DH 0x0f, -1, 2, 3
0x0000000000000000 0x000000000000000f 15
0x0000000000000008 0x000000000000ffff 65535
0x0000000000000010 0x00030002ffff000f 844437814968335
DH works with 16-bit constants and fills the lower 2 bytes of the double word.
DH fills a double word using four constants. Data Types and Assembler Commands — 20
Assembler Commands
DB 0xf ;Define Byte
DB 0x0f,-1,2,3,4,5,6,7
0x0000000000000000 0x000000000000000f 15 0x0000000000000008 0x00000000000000ff 255 0x0000000000000010 0x070605040302ff0f 506097522914295567
DB works with 8-bit constants and fills the lower 1 byte of the double word.
DB fills a double word using eight constants. Data Types and Assembler Commands — 21
Character Data
Byte-encoded character sets ASCII: 128 characters
95 graphic, 33 control
Latin-1: 256 characters
ASCII, +96 more graphic characters
Unicode: 32-bit character set
Used in Java, C++ wide characters, …
Most of the world’s alphabets, plus symbols UTF-8, UTF-16: variable-length encodings
Data Types and Assembler Commands — 22
Character Data
Data Types and Assembler Commands — 23
Assembler Commands
DB 0,1,2,3,4,5,6,7
DC “01234567”
DC “abcdefgh\0” ;\ is ╲ MEMORY 7 6 5 4 3 2 1 0
0x0000000000000000 0x0706050403020100 0x0000000000000008 0x3736353433323130 0x0000000000000010 0x6867666564636261 0x0000000000000018 0x0000000000000000
DC accepts a single constant which must be a sequence of
characters enclosed in double quotes. Include a trailing “╲0″ in the sequence of characters to make sure that it will be null-terminated irrespectively of its length.
Data Types and Assembler Commands — 24
Assembler Commands
DM 3 ;3 determines the size
0x0000000000000000 0x0000000000000000 0 0x0000000000000008 0x0000000000000000 0 0x0000000000000010 0x0000000000000000 0
DM (Define Memory in double-words): Initializes the specified number of 64-bit double-words with all 0s.
Data Types and Assembler Commands — 25
Assembler Commands
We have seen Decimal, Hexadecimal, and Character constants.
Binary and Octal constants are also available:
Binary: 0b010, 0B10
Starts with 0b or 0B and contains only the characters {01}. An optional sign can be inserted before the leading 0b or 0B.
DB 0B10 ;2(decimal)
Octal: 010, 017 (10 and 17 are decimal, not octal) Starts with 0 and contains only the digits {01234567}. An optional sign can be inserted before the leading 0.
DB 010 ;8(decimal)
Data Types and Assembler Commands — 26
Assembler Commands
ORG 0x1000
addi x5,x0,1
ASSEMBLY LISTING
ADDRESS BIN/HEX CODE
0x0000000000000800 I 000000000001 00000 000 00101 0010011 0x0000000000001000 DD 0x0000000000000001
SYMBOL TABLE
0x0000000000000800 START
TEXT SOURCE addi x5,x0,1 DD 1
ORG (Origin): Defines the address at which the next assembled data or instruction will be placed.
Data Types and Assembler Commands — 27
Byte/Halfword/Word Operations
RISC-V byte/halfword/word load Load byte/halfword/word signed:
(Sign extend to 64 bits in rd) lb rd, offset(rs1)
lh rd, offset(rs1)
lw rd, offset(rs1)
Load byte/halfword/word unsigned: (Zero extend to 64 bits in rd)
lbu rd, offset(rs1) lhu rd, offset(rs1) lwu rd, offset(rs1)
Data Types and Assembler Commands — 28
Byte/Halfword/Word Operations
RISC-V byte/halfword/word store Store byte/halfword/word:
(Store rightmost 8/16/32 bits) sb rs2, offset(rs1)
sh rs2, offset(rs1)
sw rs2, offset(rs1)
Why there is no need of unsigned versions e.g. sbu, shu, and swu?
Because there is no change in the size of the data (no expansion.)
Data Types and Assembler Commands — 29
add, addi, and sub
We have addi but no subi. Why?
An immediate value is known at compile time so the compiler can do the conversion (invert the bits and add 1)
Why do we need sub? Isn’t add enough?
A computed value is not known at compile time and it takes 2 machine instructions to convert (xori and add) which will slow the computation 3 fold.
Data Types and Assembler Commands — 30
Integer Multiplication
1. To multiply by a power of 2, e.g. 25 we shift by 5 bits to the left.
2. To multiply by any integer k we can represent k as a sum of powers of 2 e.g. if k=6 then k=22+21 and apply (1).
Therefore, multiplication by any number is essentially doing a shift corresponding to each of the powers of 2 in the representation of our number and then summing the results.
Data Types and Assembler Commands — 31
Integer Division
1. To divide by a power of 2, e.g. 25 we shift by 5 bits to the right.
2. To divide by any integer k we can still represent k as a sum of powers of 2 but unfortunately (1) cannot be directly applied to obtain the desired result.
Therefore, division by any number is essentially more complex and thus difficult to implement when compared to multiplication.
Data Types and Assembler Commands — 32
References
RVS Assembler Manual
RISC-V Instruction Set Manual
Chapter 6: ”M” Standard Extension for Integer Multiplication and Division
Data Types and Assembler Commands — 33
Floating Point (FP) Instructions
RVS Floating Point (FP) Extension Manual
Note: The only rounding mode (rm) supported in RVS and thus employed throughout the course is 000.
Data Types and Assembler Commands — 34
Floating Point (FP) Instructions
RVS Assembler Manual
Note: The only rounding mode (rm) supported in RVS and thus employed throughout the course is 000.
RISC-V Instruction Set Manual
Chapter 8: “F” Standard Extension for Single- Precision Floating-Point
Chapter 9: “D” Standard Extension for Double- Precision Floating-Point
Data Types and Assembler Commands — 35
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