CS代考 1007ICT / 1807ICT / 7611ICT Computer Systems & Networks

1007ICT / 1807ICT / 7611ICT Computer Systems & Networks
3B. Digital Logic and Digital Circuits

Last Lecture:

Topics Covered:
• Digital logic, Basic logic gates, Boolean algebra
• Combinatorial logic gates

Lecture Content
 Learning objectives
 Logic unit, Selection logic, Decoder logic  Multiplexing and demultiplexing
 Half and Full adders
© . Revised and updated by , , and Wee Lum 3

Learning Objectives
At the end of this lecture you will have gained an understanding of:
 Selection logic
 Decoder logic
 Multiplexors
 Demultiplexors
 Half and Full adders
© . Revised and updated by , , and Wee Lum 4

Logic Unit
Lets try to create a “programmable” logic unit that permits us to apply a predefined logic function to a given set of inputs.
Output Select
We need a function that lets us select what operation to perform
AND OR XOR
© . Revised and updated by , , and Wee Lum 5

Selection Logic
 Saywehaveanumberofinputs‘A,B,C,D’andwe want to select one of them to use in a logic function.
 Weneedaspecialfunctiontoswitchtheselected input into the output ‘X’ based on the selection.
 WecanuseinputsS0toS3toselectbetweenA-D
S0 S1 S2 S3
© . Revised and updated by , , and Wee Lum 6

Decoder Logic
 Justsaywewanttoselectbetweenoneof100’s of possible inputs – we need 100’s of selection inputs as well which gets too complicated.
 DecoderswithNinputsallowustoenableany one of 2N possible selection lines.
 Basicallyadecodertakesabinarycodednumber and enables the output representing the number
2 to 4 Decoder
x0 = s1ANDs2 x1 = s1ANDs2 x2 = s1ANDs2 x3 = s1ANDs2
2N outputs
© . Revised and updated by , , and Wee Lum 7

Multiplexing
 Combiningtheselectoranddecoderwecan
create what is called a
 IngeneralifwehaveNinputswewanttoswitch between we need to have log2(N) selection lines.
Multiplexor
S0 S1 selection
© . Revised and updated by , , and Wee Lum 8

Demultiplexing
We can also switch in the opposite direction to send one input ‘A’ into one of many different outputs (eg X1..Xn)
Input X1 A X2
outputs X4
(s0,s1) Select
S0 S1 selection
© . Revised and updated by , , and Wee Lum 9

Half-Adders
In addition to logic functions we can also create maths functions.
The simplest math function is the half-adder which can add 2 digits (bits) to give a sum and a carry bit
0011A 0 1 0 1B+ 0 1 1 10
Sum = A XOR B Carry = A AND B
© . Revised and updated by , , and Wee Lum 10

Full-Adders
 Ifwewanttoaddmorethan1bitvaluestogether we need to deal with the carry.
 Full-addersacceptthetwoinputstobeaddedplus the carry from a previous stage.
 Thecircuitmustbeabletodealwithpropagation delays
00 00 01 01 00 10 11 11A 00 01 00 01 10 01 10 11B+ 00 01 01 10 10 11 101 110
A0 B0 A1 B1 A2 B2 A3 B3
Full Adder
Full Adder
Full Adder
Full Adder

S0 S1 4 bit adder S2 S3 © . Revised and updated by , , and Wee Lum -Adders
The logic to perform add with carry combines two half adders together.
Sum =AXORBXOR = (AANDB)OR(CinAND(AXORB))
© . Revised and updated by , , and Wee Lum 12

Subtraction
 A–BisthesameasA+(-B)
 IfweconvertBtothenegativeequivalentofits value, we can use the basic adder as it is. We can use an XOR gate to do this.
 However,convertingBto–Busingtwo’s complement also requires adding 1
A B0 Sign bit 0
+0 if positive +1 if negative
Full Adder
© . Revised and updated by , , and Wee Lum 13

Have considered:  Selection logic  Decoder logic
 Multiplexors
 Demultiplexors
 Half and Full adders
© . Revised and updated by , , and Wee Lum 14

 Arithmetic logic unit
 Binary multiplication and division
 Shifting
 Sequential Logic
 Data latches, S-R Latch
 Clocks and synchronisation
 Registers, Buses, Computer memory  Processors and Memory Organisation
© . Revised and updated by , , and Wee Lum 15

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