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Using the ModelSim-Intel FPGA Simulator with VHDL Testbenches
For Quartus® Prime 18.0
1 Introduction
This tutorial introduces the simulation of VHDL code using the ModelSim-Intel FPGA simulator. We assume that you are using ModelSim-Intel FPGA Starter Edition version 18.0. This software can be downloaded and installed from the Download Center for Intel FPGAs. In this download center, you can select release 18.0 of the Quartus PrimeLiteEdition,andthenontheIndividual FilestabchoosetodownloadandinstalltheModelSim-Intel FPGA Starter Edition software. We assume that you are using a computer that is running the Windows operating system. If you are using the Linux operating system then minor differences to the instructions would apply, such as using a / filesystem delimiter rather than the \ delimiter that is used with Windows.

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• Getting Started with ModelSim
• Simulating a Sequential Circuit
• Simulating a Circuit that Includes a Memory Module • Setting up a ModelSim Simulation
• Using the ModelSim Graphical User Interface
Requirements:
• ModelSim-Intel FPGA Starter Edition software
• AcomputerrunningeitherMicrosoft*Windows*(version10isrecommended)orLinux(Ubuntu,orasimilar Linux distribution). The computer would typically be either a desktop computer or laptop, and is used to run the ModelSim software.
• Intel Quartus® Prime software
• A DE-series development and education board, such as the DE1-SoC board. These boards are described on Intel’s FPGA University Program website, and are available from the manufacturer Terasic Technologies.
Intel Corporation – FPGA University Program 1 June 2018

USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 2 Getting Started
The ModelSim Simulator is a sophisticated and powerful tool that supports a variety of usage models. In this tutorial we focus on only one design flow: using the ModelSim software as a stand-alone program to perform functional simulations, with simulation inputs specified in a testbench, and with simulator commands provided via script files. Other possible design flows for using ModelSim include invoking it from within the Intel Quartus Prime software, performing timing simulations, and specifying simulation inputs by drawing waveforms in a graphical editor instead of using a testbench. These flows are described in other documentation that is available on the Internet.
To introduce the ModelSim software, we will first open an existing simulation example. The example is a multibit adder named Addern, and is included as part of the design files provided along with this tutorial. Copy the Addern files to a folder on your computer, such as C:\ModelSim_Tutorial\Addern. In the Addern folder there is a VHDL source-code file called Addern.vhd and a subfolder named ModelSim. The Addern.vhd file, shown in Figure 1, is the VHDL code that will be simulated in this part of the tutorial. We will specify signal values for the adder’s inputs, Cin, X, and Y, and then the ModelSim simulator will generate corresponding values for the outputs, S and Cout.
library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_signed.all;
ENTITY Addern IS
GENERIC (n : INTEGER := 16);
PORT ( X, Y : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
Cin : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0); Cout : OUT STD_LOGIC);
END Addern;
ARCHITECTURE Behaviour OF Addern IS
SIGNAL Sum : STD_LOGIC_VECTOR(n DOWNTO 0);
Sum <= (’0’ & X) + (’0’ & Y) + Cin; S <= Sum(n-1 DOWNTO 0); Cout <= Sum(16); END Behaviour; Figure 1. VHDL code for the multibit adder. We will use three files, included in the ModelSim subfolder, to control the ModelSim simulator. The files are named testbench.vht, testbench.tcl, and wave.do. The testbench.vht file is a style of VHDL code known as a testbench. The purpose of a testbench is to instantiate a VHDL entity that is to be simulated, and to specify values for its inputs at various simulation times. In this case the module to be simulated is our multibit adder, which we refer to as the design under test (DUT). Line 5 is the start of the testbench entity, which has no inputs or outputs. Line 9 declares the Addern component, which will be instantiated later in the testbench code. In Lines 16 to 18 we declare signals to drive the adder inputs Cin, X, and Y. Lines 19 and 20 declare signals to connect to the adder outputs S and Cout. 2 Intel Corporation - FPGA University Program June 2018 USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 Lines 22 to 36 provide a process labeled vectors that is used to specify the values of the adder inputs. First, in Line 24 the adder inputs X, Y, and Cin are set to 0. The next line of code waits until 20 ns of simulation time has passed, and then line 26 changes the input Y to the 10. Following another 20 ns of waiting time, meaning at 40 ns in simulation time, line 28 changes the input X to 10. The rest of the process specifies various values for the adder inputs at 20 ns time increments. Finally, in Line 38 the testbench entity instantiates the Addern entity. Its inputs are driven by the testbench signal values specified in the vectors process. 1 LIBRARY ieee; 2 USE ieee.std_logic_1164.all; 3 USE ieee.std_logic_signed.all; 5 ENTITY testbench IS 6 END testbench; 8 ARCHITECTURE Behavior OF testbench IS 9 COMPONENT Addern 10 PORT ( 11 X,Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); Cout : OUT STD_LOGIC ); 14 END COMPONENT; 15 16 SIGNAL Cin : STD_LOGIC; 17 SIGNAL X : STD_LOGIC_VECTOR(15 DOWNTO 0); 18 SIGNAL Y : STD_LOGIC_VECTOR(15 DOWNTO 0); 19 SIGNAL S : STD_LOGIC_VECTOR(15 DOWNTO 0); 20 SIGNAL Cout : STD_LOGIC; 22 vectors: PROCESS 24 X <= X"0000"; Y <= X"0000"; Cin <= ’0’; 25 WAIT FOR 20 ns; 26 Y <= X"000A"; Cin <= ’0’; 27 WAIT FOR 20 ns; 28 X <= X"000A"; Cin <= ’0’; 29 WAIT FOR 20 ns; 30 Cin <= ’1’; 31 WAIT FOR 20 ns; 32 X <= X"FFF0"; Y <= X"000F"; Cin <= ’0’; 33 WAIT FOR 20 ns; 34 Cin <= ’1’; 36 END PROCESS; 38 U1: Addern PORT MAP (X, Y, Cin, S, Cout); Figure 2. The VHDL testbench code. Intel Corporation - FPGA University Program 3 June 2018 USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 Open the ModelSim software to reach the window shown in Figure 3. Click on the Transcript window at the bottom of the figure and then use the cd command to navigate to the ModelSim folder for the multibit adder. For example, inourcasewewouldtypecd C:/ModelSim_Tutorial/Addern/ModelSim.NotethatModelSimusesthe / symbol to navigate between filesystem folders, even though the Windows operating system uses the \ symbol for this purpose. Next, we wish to run a series of simulator commands that are included in the script file testbench.tcl. Figure 3. The ModelSim window. Figure 4 shows the contents of the script testbench.tcl. First, the quit command is invoked to ensure that no simulation is already running. Then, in Line 4 the vlib command is executed to create a work design library; ModelSim stores compilation/simulation results in this working library. The VHDL compiler is invoked in Line 7 to compile the source code for the Addern entity, which is in the parent folder (../), and in Line 8 to compile testbench.vht in the current folder. The simulation is started by the vsim command in Line 9. It includes some simulation libraries for Intel FPGAs that may be needed by ModelSim. If the included libraries aren’t required for the current design, then they will be ignored during the simulation. Line 10 in Figure 4 executes the command do wave.do. The do command is used to execute other ModelSim commands provided in a file. In this case the file wave.do, which will be described shortly, contains various commands that are used to configure the ModelSim waveform-display window. The final command in Figure 6 advances the simulation by a desired amount of time, which in this case is 120 ns. 4 Intel Corporation - FPGA University Program June 2018 USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 To run the script, in the Transcript window type the command do testbench.tcl. ModelSim will execute the commands in this script and then update its graphical user interface to show the simulation results. The updated ModelSim window after running the testbench.tcl script is illustrated in Figure 5. 1 # stop any simulation that is currently running 2 quit -sim 3 # create the default "work" library 4 vlib work; 6 # compile the VHDL source code, and the testbench 7 vcom ../*.vhd 8 vcom *.vht 9 vsim work.testbench -Lf 220model -Lf altera_mf 10 do wave.do 11 run 120 ns Figure 4. The testbench.tcl file. Figure 5. The updated ModelSim window. Intel Corporation - FPGA University Program 5 June 2018 Intel Corporation - FPGA University Program USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 The wave.do file used for this design example appears in Figure 6. It specifies in Lines 3 to 12 which signal waveforms should be displayed in the simulation results, and also includes a number of settings related to the display. To add or delete waveforms in the display you can manually edit the wave.do file using any text editor, or you can select which waveforms should be displayed by using the ModelSim graphical user interface. Referring to Figure 5, changes to the displayed waveforms can be selected by right-clicking in the waveform window. Waveforms can be added to the display by selecting a signal in the Objects window and then dragging-and-dropping that signal name into the Wave window. A more detailed discussion about commands available in the graphical user interface is provided in Appendix A. Quit the ModelSim software to complete this part of the tutorial. To quit the program you can either select the File > Quit command, or type exit in the Transcript window, or just click on the X in the upper-right corner of the ModelSim window.
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -label Cin /testbench/Cin
4 add wave -noupdate -label X -radix hexadecimal
5 add wave -noupdate -label Y -radix hexadecimal
6 add wave -noupdate -label Cout /testbench/Cout
7 add wave -noupdate -divider Adder
8 add wave -noupdate -label Cin /testbench/U1/Cin
9 add wave -noupdate -label X -radix hexadecimal /testbench/U1/X
10 add wave -noupdate -label Y -radix hexadecimal /testbench/U1/Y
11 add wave -noupdate -label Sum -radix hexadecimal /testbench/U1/Sum 12 add wave -noupdate -label Cout /testbench/U1/Cout
13 TreeUpdate [SetDefaultTree]
14 WaveRestoreCursors {{Cursor 1} {20000 ps} 0}
15 quietly wave cursor active 1
16 configure wave -namecolwidth 73
17 configure wave -valuecolwidth 64
18 configure wave -justifyvalue left
19 configure wave -signalnamewidth 0
20 configure wave -snapdistance 10
21 configure wave -datasetprefix 0
22 configure wave -rowmargin 4
23 configure wave -childrowmargin 2
24 configure wave -gridoffset 0
25 configure wave -gridperiod 1
26 configure wave -griddelta 40
27 configure wave -timeline 0
28 configure wave -timelineunits ns
30 WaveRestoreZoom {0 ps} {120 ns}
Figure 6. The wave.do file.
/testbench/X
/testbench/Y

USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0
3 Simulating a Sequential Circuit
Another ModelSim example, called Accumulate, is included as part of the design files for this tutorial. Copy the Accumulate example to a folder on your computer, such as C:\ModelSim_Tutorial\Accumulate. In the Accumulate folder there is a VHDL source-code file called Accumulate.vhd and a subfolder named ModelSim. The Accumu- late.vhd file, which provides the VHDL code that we will simulate, is shown in Figure 7. It represents the logic circuit illustrated in Figure 8, which includes an adder, register, and down-counter. The purpose of this circuit is to add together, or accumulate, values of the input X for each clock cycle until the counter reaches zero.
ENTITY Accumulate IS
PORT ( KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLOCK_50 : IN STD_LOGIC;
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END ENTITY;
ARCHITECTURE Behaviour OF Accumulate IS
SIGNAL X, Y, Count : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL Clock, Resetn, z : STD_LOGIC;
SIGNAL Sum : STD_LOGIC_VECTOR(9 DOWNTO 0);
Clock <= CLOCK_50; X <= SW(4 DOWNTO 0); Y <= SW(9 DOWNTO 5); Resetn <= KEY(0); PROCESS (Clock, Resetn, z) BEGIN IF Resetn = ’0’ THEN Sum <= "0000000000"; -- define the Sum register ELSIF Clock’EVENT AND Clock = ’1’ AND z = ’1’ THEN Sum <= Sum + ("00000" & X); END IF; END PROCESS; PROCESS (Clock, Resetn, Y, z) -- define the down-counter BEGIN IF Resetn = ’0’ THEN Count <= Y; ELSIF Clock’EVENT AND Clock =’1’ AND z = ’1’ THEN Count <= Count - "00001"; END IF; END PROCESS; z <= Count(0) OR Count(1) OR Count(2) OR Count(3) OR Count(4); LEDR <= Sum(9 DOWNTO 0); END Behaviour; Figure 7. VHDL code for the accumulator. Intel Corporation - FPGA University Program 7 June 2018 USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 The Accumulate entity in Figure 7 has ports KEY, CLOCK_50, SW, and LEDR because it is intended to be im- plemented on a DE-series board that features an Intel FPGA, such as the DE1-SoC board. After simulating the VHDL code to verify its correct operation, you may wish to compile it using the Quartus Prime CAD tools and then download and test the resulting circuit on a board. A testbench.vht file for the accumulator design under test (DUT) is given in Figure 9. Three signals, KEY, CLOCK_50, and SW are declared to provide inputs to the DUT, as well as a signal LEDR for connecting to the DUT outputs. The Accumulate entity is instantiated in Line 17. It is useful to define a periodic signal that can be used as a clock input for the Accumulate sequential circuit. We could manually define some number of cycles for such a signal in a process, but this method would be awkward. Instead, Lines 19 to 25 in Figure 9 show how to make a periodic signal by specifying just one period. This process gets executed repeatedly, because it does not end with a sepatate WAIT statement. Thus, the CLOCK_50 signal is inverted every 10 ns in simulation time to create a 50 MHz periodic waveform. This clock process is executed concurrently by the Simulator along with the process in Lines 27 to 36. This process sets KEY0 = 0 and SW= 0 at the start of the simulation, which allows the Sum in the accumulator to be cleared. At 20 ns in simulation time SW9−5 is set to 10, so that this value can be loaded into the counter. Finally, at 40 ns in simulation time KEY0 is set to 1 and SW4−0 is set to 30, so that this value can be accumulated for each clock cycle until the counter reaches 0. L Down-Counter Resetn Register Figure 8. The accumulator circuit. Reopen the ModelSim software to get to the window in Figure 3. Click on the Transcript window at the bottom of the figure and then use the cd command to navigate to the ModelSim folder for the accumulator. For example, inourcasewewouldtypecd C:/ModelSim_Tutorial/Accumulate/ModelSim.Then,intheTranscript windowtypethecommanddo testbench.tclasyoudidforthepreviousexample.Thetestbench.tclscriptfor thisexampleisidenticaltotheoneshowninFigure4,exceptthatthelastlinespecifiesrun 300 ns. 8 Intel Corporation - FPGA University Program June 2018 Accumulate PORT MAP (KEY, SW, CLOCK_50, LEDR); clock_process: PROCESS BEGIN WAIT FOR PROCESS; USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 1 ENTITY testbench IS 2 END testbench; 4 ARCHITECTURE Behavior OF testbench IS 5 COMPONENT Accumulate KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0); SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLOCK_50 : IN STD_LOGIC; LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); 10 END COMPONENT; 11 12 SIGNAL CLOCK_50 : STD_LOGIC; 13 SIGNAL KEY : STD_LOGIC_VECTOR(0 DOWNTO 0); 14 SIGNAL SW : STD_LOGIC_VECTOR(9 DOWNTO 0); 15 SIGNAL LEDR : STD_LOGIC_VECTOR(9 DOWNTO 0); vectors: PROCESS BEGIN KEY(0) <= ’0’; SW <= "0000000000"; WAIT FOR 20 ns; SW(9 DOWNTO 5) <= "01010"; WAIT FOR 20 ns; SW(4 DOWNTO 0) <= "11110"; KEY(0) <= ’1’; Figure 9. The VHDL testbench code for the sequential circuit. The simulation results for our sequential circuit, which display the waveforms selected in its wave.do file, appear in Figure 10. In this figure the SW and LEDR signals are displayed in hexadecimal, while X, Sum, Y, and Count are displayed as unsigned (decimal) values. The Sum is cleared by the clock edge at 10 ns, and the Count is initialized to 10 at 30 ns. Starting with the clock edge at 50 ns the value X = 30 is accumulated until the counter reaches 0. Quit the ModelSim software to complete this part of the tutorial. Intel Corporation - FPGA University Program 9 June 2018 USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 Figure 10. The simulation results for our sequential circuit. 4 Simulating a Circuit that Includes a Memory Module The design files archive provided along with this tutorial includes a ModelSim example called Display. It shows how to instantiate a memory module in VHDL code, and how to initialize the stored contents of the memory in a ModelSim simulation. Copy the Display files to a folder on your computer, such as C:\ModelSim_Tutorial\Display. In the Display folder there is a file called Display.vhd that provides the VHDL code that we will simulate, and a subfolder named ModelSim. Figure 11 shows the VHDL code for Display.vhd. Its ports are named KEY, SW, HEX0, and LEDR because the entity is intended to be implemented on a DE-series board that features an Intel FPGA, such as the DE1-SoC board. After simulating the VHDL code to verify its correct operation, you may wish to compile it using the Quartus Prime CAD tools and then download and test the resulting circuit on a board. Figure 12a gives a logic circuit that corresponds to the code in Figure 11. The circuit contains a counter that is used to read the contents of successive addresses from a memory. This memory provides codes in ASCII format for some upper- and lower-case letters, which are provided as inputs to a decoder entity. The counter and memory module have a common clock signal, and the counter has a synchronous clear input. Each successive clock cycle advances the counter and reads a new ASCII code from the memory. Since the counter is three-bits wide, only the first eight locations in the memory are read (the upper two address bits on the memory are set to 00), and they provide the ASCII codes for letters A, b, C, d, E, F, g, and h. The decoder produces an appropriate bit-pattern to render each letter on a seven-segment display. The memory used in the logic circuit is depicted in part b of Figure 12. It is a 32 × 8 synchronous read-only memory (ROM), which has a register for holding address values. The memory is initialized with the contents of the file inst_mem.mif, which is illustrated in Figure 13. This file contains the ASCII codes for the eight letters displayed by the circuit. 10 Intel Corporation - FPGA University Program June 2018 USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VHDL TESTBENCHES For Quartus® Prime 18.0 ENTITY display IS PORT ( KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0); SW : IN STD_LOGIC_VECTOR(0 DOWNTO 0); HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END ENTITY; ARCHITECTURE Behavior OF display IS COMPONENT inst_mem PORT ( address clock q END COMPONENT; : IN STD_LOGIC_VECTOR (4 DOWNTO 0); : IN STD_LOGIC ; : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); COMPONENT count3 PORT ( Resetn, Clock : IN STD_LOGIC; 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com