CS代写 CS 343, Spring 2022

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators

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(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Objective:
Using comparators (1-bit, 2-bit, 8-bit), this lab covers the following:
1. Introduction to VHDL, Design Comparator, and test it.
2. Introduction to ModelSim for circuit simulation (Learn How to use Model-Sim to simulate
comparator)
3. Testing of circuits using a test bench file
4. Your task: Assignment for you to perform once completed the design, simulation and testing
part of this lab tutorial. It also includes an outline for you to use in your lab report.
VHDL is intended for describing and modeling a digital system at various levels and is an extremely complex language. Then, we will use the design tool ModelSim to design, and verify our VHDL designs. Modelsim is widely used in industry
Tasks to Perform:
You should use Quartus version 20.0 and up.
• PROJECT NAME, DIRECTORY NAME, COMPONENTS, input output ports YOU ARE DESIGNING NAMES SHOULD HAVE AS A PREFIX YOUR LAST NAME AND DATE.
• Complete QUARTUS window showing version and directory name should be displayed with every screenshots.
NOTE: In this lab you will design 1-bit, 2-bit and 8-bit comparators; however, we will only show you
how to do the simulation. The 2-bit and 8-bit comparators follow the exact same procedure and are
left for you to execute.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
• All code and waveforms have to be shown in Quartus , Modelsim windows.
• No typed code or waveform will be accepted. If you choose to do so, your project is nullified
(zero grade)
TASK 0: Complete tutorial as listed below.
Task 1: 1a. write vhdl code for 2 bit comparator compile it, 1b Verify correctness of 2 bit
comparator using Model-SIM using tutorial.
Task 2: 2a. write vhdl code for 8 bit comparator compile it, 2b Verify correctness of 8 bit comparator using Model-SIM.
Additional Tasks:
Task A1. Optimize the 1 bit comparator VHDL code shown on page 3, to replace lines 12,13,14 with ONE Boolean operation!
Task A2. Optimize other comparators accordingly.
Task A3. Design and test using Model_Sim optimized 2 and 8 bit comparators in VHDL.
Please list each task as HEADER in your submission. If you did not the task please write task number and
sentence I DID NOT DO task #.
YOU ARE NOT ALLOWED TO COPY anything (CODE OR FIGURES) FROM THIS HANDOUT.
IF YOU DO COPY, this may result in ZERO grade.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
1. INTRODUCTION TO VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. It is a language used in electronic design automation to describe digital and mixed-signal systems such as field- programmable gate arrays and integrated circuits. For VHDL primer please refer to this link
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html
Basic VHDL Example:
One-bit Comparator Design
1-BIT COMPARATOR

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
A one bit comparator is a circuit that can be used to compare two one-bit signals. The comparator outputs a ‘1’ if the input signals are equal; otherwise, the comparator outputs a ‘0’.
As introduction to this course, we use a simple comparator to illustrate the skeleton of a VHDL program. The description uses only logical operators and represents a gate-level combinational circuit, which is composed of simple logic gates.
Input Output i0 i1 Eq
001 010 100 111
Figure 5. Truth table of a 1-bit comparator
The truth table can be expressed by the following equation: Eq=i0.i1 + i0’ .i1’

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
The entire code for the 1-bit comparator is shown below:
6 Eq : out std_logic); 7 end equal;
Library ieee;
use ieee.std_logic_1164.all;
entity equal is
port ( I0, I1 : in std_logic;
architecture arch of equal is signal p0, p1 : std_logic;
EQ <= p0 or p1; p0 <= (not I0) and (not I1); p1 <= I0 and I1; CS 343, Spring 2022 Laboratory Project 2 Introduction to VHDL, ModelSim and Quartus using Comparators (Detailed version) Instructor: Professor Izidor Gertner February 23, 2022 Due date: February 27, 2022 by 11:00 PM Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report. As we said before, VHDL is case insensitive, which means that upper and lowercase letters can be used interchangeably, and free formatting, which means that spaces and blank lines can be inserted freely. Lines 1 and 2 tell the compiler (in our case Quartus and ModelSim) which libraries to use. The libraries contain precompiled VHDL code. For example ieee.std_logic_1164.all contains the code for the ‘or’ function, and without it the VHDL compiler would generate and error on line 12. Lines 4 to 7 are the entity declaration statements. The entity declaration outlines the input and output signals of the circuit. The mode term can be in or out, which indicates that the corresponding signals flow “into” or “out of” of the circuit. It can also be inout, for bidirectional signals. Lines 9 to 15 are the architecture statements. The architecture body describes functions of the circuit. The architecture may include signals which we have used in line 10. We need the signals to store the value of first product and second product. You will understand signals more as you do more coding. The main description, encompassed between begin and end, contains three concurrent statements. Unlike a program in C language, in which the statements are executed sequentially, concurrent statements are like circuit parts that operate in parallel. The signal on the left-hand side of a statement can be considered as the output of that part, and the expression specifies the circuit function and corresponding input signals. Notice that to translate our equation into VHDL code, we represented the term i0 . i1 as p0, and the term i0’ . i1’ as term p1. Then we say Eq = p0 + p1. We can, of course, represent the equation in just one line of VHDL code; however, as our codes grow larger, it is better to break our assignments to make the code more readable and modular. This notion will become apparent as you work on bigger projects. NOTE: Just like we have an Eq output, we can also have a notEq output that notifies when the inputs being compared are not equal. This is left for you as an exercise after you complete the tutorial part of this lab. See the YOUR TASK section towards the end of this lab for further explanation. CS 343, Spring 2022 Laboratory Project 2 Introduction to VHDL, ModelSim and Quartus using Comparators (Detailed version) Instructor: Professor Izidor Gertner February 23, 2022 Due date: February 27, 2022 by 11:00 PM Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report. 2. INTRODUCTION TO MODELSIM 2.1 ModelSim installation: ModelSim is a multi-language HDL simulation environment by Mentor Graphics, for simulation of hardware description languages such as VHDL and Verilog. Simulation is performed using the graphical user interface (GUI), or automatically using scripts. For this part you must have ModelSim installed in your computer. Altera gives you the choice to download ModelSim as bundle when you download Quartus from their website. • If you followed our tutorial on installing Quartus and ModelSim, you are ready to go and you can ignore the bullet point bellow. (Alternatively, if you haven’t installed any of these programs, please follow our tutorial on Quartus and ModelSim download and setup, then come back to this lab). • If you have Quartus installed but not ModelSim, you can download it independently from their website, just make sure you choose the same version of Quartus you already have in your computer before starting download. Go to: https://fpgasoftware.intel.com/?edition=pro&product=modelsim_ae%23tabs-2 The following shows the download page from Altera. It is important that you know which version of Quartus you have installed in your computer. If you don’t know, open up Quartus, then go to Help > About Quartus II

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 6. Screenshot of our Quartus version.
Our version is 13.0 service pack 1, yours may be different.
The next screenshot shows the download page for the Quartus software. Notice that at the top it says Subscription Edition although you may have downloaded the Free Web edition. This is irrelevant: it doesn’t matter if it is part of the FREE or SUBSCRIPTION edition, ModelSim as a component is the same for both editions. Make sure you are logged into your Altera account (since you installed Quartus, we assume you have an account already with them).

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 7. ModelSim download page
2.1 ModelSim basics:
1. Open ModelSim. To run ModelSim, go to terminal and type vsim. This tutorial was done on a Windows environment, so we will show the corresponding Windows system screenshots but other operating systems should follow similar steps.
If you are on Windows go to Start > Run. Type in “cmd” (without quotes) in the input field, then hit Enter. Alternatively, you could also search for Command Prompt in the search field in the Start Menu.
If you are on Linux, right click your desktop and click Terminal.
Figure 8. Run Command in Windows

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
In terminal type “vsim” (without the quotes).
Figure 9. Terminal and ModelSim start command
You are now taken to the main screen of ModelSim, a Welcome splash screen will appear and you are now ready to start testing your circuit designs.
The initial screen of ModelSim is shown below:

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 10. ModelSim Welcome screen
3. When the Welcome screen appears, hit Close. Now go to Now go to File > New > Project. If a message appears asking if you want to close the current project just accept.
4. The Create dialog appears, enter a name for your project, you can call it one_bit_comparator. See figure 11.
5. Browse a location for your new project.
6. In the Default Library Name, if empty, call it work.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 11. Create dialog in ModelSim
7. The Add items to project dialog appears (See figure 12). In the previous section we described the comparator we are going to implement and we gave you the VHDL code for it. Right now we are going to create a new VHDL file and copy-paste the given code to it. Click Create .

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 12. Add items dialog
8. The Create Project File dialog appears, see figure below. In the File Name field enter equal, then hit OK.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 13. Create Project File dialog
9. Right click the file equal.vhd you just included, and then choose Edit.
Figure 14. Project navigator in ModelSim with the equal.vhd file

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
10. A panel with a code editor appears. Copy and paste the code given in the previous section of this lab for the one-bit comparator, called equal.vhd
11. Save this file by going to File > Save.
12. In the project navigation panel, right click the equal.vhd file and choose Compile > Compile
Figure 15. Code editor in ModelSim and Compilation options
13. At the bottom of the main ModelSim window you should see a Transcript panel, it will output a message to notify you if the compilation was successful or of any errors. Also, next to the name

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
of your file you should see a if the file is compiled or a Blue Question Mark if it is not.
Figure 16. Transcript panel – Compilation successful
14. Go to Simulate > Start Simulation…
15. A dialog appears, browse the “work” Library which is (by default) the library we told ModelSim
to store the file we wanted to have imported. Select the equal entity and click OK.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 17. Choosing equal entity which will be simulated
Note: at this stage you are allowed to select multiple files, let’s say if you had a one-bit-comparator and a two-bit comparator and want to simulate and compare both, if you have the VHDL files ready in your work Library you can select both and they will be included in your simulation configuration. For now we only have a equal.vhd file which is our one-bit comparator, so we are adding only one file.
16. ModelSim should arrange its layout automatically to allow for simulation. At this point you should have something similar to figure 18. With your mouse, select the one-bit comparator inputs (i0 and i1) and output (Eq) and drag them to the wave panel as you see in the picture:

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 18a. Dragging inputs and outputs to waveform panel
Alternatively, you could also right click on the name of the VHDL file as shown in Figure 18b and click Add Wave

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 18b. Adding inputs and outputs through menu to waveform panel
17. Now that you have your inputs and outputs in the waveform, it is time to give them values to simulate. Note that a “U” (Undefined) appears to every input/output of your wave list. This means that no value has been set for these. To give a value to an input signal, right click the first input (i0) then select Force.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim and Quartus using
Comparators
(Detailed version)
Instructor: Professor Izidor Gertner February 23, 2022
Due date: February 27, 2022 by 11:00 PM
Submit Complete Report, including screenshots with explanations, and VHDL code in Quartus and Modelsim windows. NO VIDEO for this report.
Figure 19. Force values option
18. When the dialog appears, change the Value from U (undefined) to 0. Click OK.

CS 343, Spring 2022
Laboratory Project 2
Introduction to VHDL, ModelSim

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