COMP2300/6300
Computer Organisation and Program Execution
ALU Operations
Dr Charles 1, 2022
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Week 2: ALU operations
a tour of your microbit Instructions
Fetch-Decode-Execute Condition flags
A tour of your microbit
There’s lots of stu on your microbit
Way more than you can master in a one-semester course…
… but youʼll understand a lot more about it by the end of the course than you do now
Instructions
Recap: a 32-bit register
Itʼs just a bunch of sequential (stateful) circuits hooked up to a common clock line (like we discussed last week)
Moar registers!
Registers are usually grouped in banks (groups). Here are the 16 general-purpose registers in your microbitʼs CPU
Backto1+2,butthistime,inC
int x = 1 + 2;
How do you think this might work in silicon?
How does this relate to the gates and things that we looked at last week?
Breaking it down
int x = 1 + 2;
So, there are three steps: 1. get a 1 into a register
2. get a 2 into another register
3. tell the ALU to add them and put the result into another register
First assembly code
@ move a 1 into r0
movs r0, 1
@ move a 2 into r1
movs r1, 2
@ add them together, put result in r2
adds r2, r0, r1
Let’s do it for reals
Addition in machine code
adds
The add instruction is encoded into this 16-bit value
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0001100mmmnnnddd
the 0001100 part is the operation code (opcode) the other parts (m, n, d) are the arguments
Example: addition in machine code
adds r2, r0, r1
Here, Rd is r2, Rn is r0 and Rm is r1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0001100mmmnnnddd
So what does the instruction look like?
15 14 13 12 11 10 9876543210 0001100001000010
Back to the ALU, how would this code fit?
15 14 13 12 11 10 9876543210 0001100001000010
Assembly code vs machine code
Thereʼs a direct mapping between the two, although the microbit only understands the machine code (of course!)
We use assembly code because:
itʼs easier for humans to read/write
it gives a little bit of flexibility (as weʼll see shortly)
The assembler
The word assembly/assembler is way overloaded in computer architecture. It might mean
the human-readable assembly code, e.g.
adds r2, r0, r1
the program for encoding that human-readable statement into the binary machine code
(the 1s and 0s)
the process of doing that conversion
GNU Assembler
The toolchain we use in this course uses GAS: the GNU Assembler (part of binutils)
The assembler determines the acceptable syntax for your assembly .S files (there are multiple syntaxes—thereʼs no one “assembly language”, even for a specific board)
So, registers are just like variables… right? Discuss with your neighbour
The move instruction
Ok, letʼs get back to our 1 + 2 program. lets us add the numbers in the registers, but how do we get the numbers (i.e. 1 and ) into the program?
movs
15 14 13 12 11 10 9876543210
00100dddiiiiiiii The clever idea: store the immediate value inside the instruction!
if this is the move instruction:
15 14 13 12 11 10 9876543210 00100dddiiiiiiii
what does the following instruction do?
15 14 13 12 11 10 9876543210 0010010000001101
So what instructions are possible?
Thatʼs determined by the Instruction Set Architecture (ISA)
Also specifies the number & size of the registers, memory and a few other things Many CPUs share the same instruction set (thatʼs kindof the point)
ARM Cortex-M series CPU From the ARM website:
“The Arm Cortex-M processor family is a range of scalable, energy e icient and easy- to-use processors that meet the needs of tomorrowʼs smart and connected embedded applications
The microbit has a Cortex-M4 CPU
ARMv7 reference manual
The microbit (like all Cortex-M series processors) uses the ARMv7-M ISA
Youʼll be looking at this a lot in the course—whenever you need more info than the cheat sheet provides
The COMP2300 cheat sheet
Itʼs available from the resources page
Understanding the instruction syntax
add{s} {
anything inside curly brackets {} is optional
anything inside angle brackets <> is a placeholder for di erent argument values register arguments Rn / Rm / Rd youʼve seen already (e.g. r3 )
Understanding the instruction syntax
add{s} {
the optional specifies an instruction width ( n / w )
{,
Assembler syntax: optional arguments
Sometimes the syntax specifies that a register argument is optional
This doesnʼt mean that those bits are missing from the encoding!
Instead, it means that the registers are re-used (overwriting what was there before)
You’ll learn the syntax by using it Especially in labs!
Reduced Instruction Set Computing (RISC) is an approach to ISA design where there are only a few instructions, and to do more complex things you just “chain them together”
The R in ARM stands for RISC
There are other options: CISC (Complex Instruction Set Computing)
Multi-width instructions
Your microbit actually supports a few di erent encodings for some instructions
All Cortex-M processors run in Thumb-2 mode, which includes both 16-bit and 32-bit instructions (youʼll examine this in lab 2)
The registers are always 32-bit, though
So many names!
ARM, Cortex, M, Thumb-2, oh my!
Some of this stu was designed (well) from the start, some was added later… There are 100+ billion of these things out there—some diversity is to be expected
The reference manual
Thereʼs a full list of all instructions & encodings in the ARM®v7-M Architecture Reference
Manual, section 7.7 (starting on p184)
Itʼs got all the gory details
Letʼs find the mov instruction…
Instructions: Part 2
Immediate vs register instructions
Some instructions require register “arguments”: places where the bits in the encoded instruction specify which registers to read from/write to.
adds r2, r0, r1
Other instructions have immediate values ( #
value is encoded in the instruction.
movs r0, 1
Some folks have been looking through the reference manual, and noticed that some instructions have both an immediate version and a register version
Example: add
Hereʼs add (immediate) (encoding T2, A7.7.3 in the reference manual)
15 14 13 12 11 10 9876543210 00110dddiiiiiiii
Hereʼs add (register) (encoding T1, A7.7.4 in the reference manual)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0001100mmmnnnddd
why do we need both immediate and register versions of these instructions?
Instructions == the language of the CPU
s encode the instruction
the CPU understands them (if theyʼre part of the language it speaks, i.e. the ISA) the CPU does exactly what itʼs told at that moment
but what about the next moment? And the one a er that?
Fetch-decode-execute cycle
Recap: ARMv7-M registers
the pc register
Register 15 ( r15 ) is a bit special in this ISA—itʼs the program counter
Imagine all the instructions in your program are lined up, one a er the other… the program counter is like a bookmark keeping track of where the CPU is up to
(for where the instructions are lined up, wait till next week)
Fetch-decode-execute
During execution, your microbit:
1. fetches the next instruction based on pc
2. decodes which operation ( add , sub , etc.) to perform (and on which registers) 3. executes the instruction
then it goes back to step 1 and repeats the process the fetch-decode-execute cycle
Status flags
whatʼs with the s in adds
Where does the final “carry out” go?
Remember last week we wondered where the last “carry” bit goes in our ripple carry adder? Answer: the carry flag/bit (in the status register)
Program status register
The ARMv7-M ISA specifies a program status register (PSR) for keeping track of various important bits of state associated with the current computation
The 4 highest bits ( 31 : 28 ) are the NZCV flags:
Negative Zero Carry Overflow
In VSCodium
“Set flags” instructions
If thereʼs an s on the end of the instruction, it means that the instruction will set the flags (if appropriate) based on the result of the instruction
This is specified by a certain bit in the encoding (in some of the encodings, anyway) You donʼt have to set flags—the s is optional
Recap: natural (unsigned) & twos-complement (signed) binary numbers
Think of the velodrome
The twos complement “circle”
This status flag is set when the result of an ALU operation is negative if interpreted as a twos complement signed integer
movs r0, 5
movs r1, 6
subs r2, r0, r1
donʼt forget the s su ix
movs r0, 5
movs r1, 6
subs r2, r0, r1
What flags will be set a er the subs instruction is executed?
We’ll demo all of these, just to be sure!
This status flag is set when the result of an ALU operation is zero
movs r5, 5
movs r6, -5
adds r4, r5, r6
This status flag is set when the result of an ALU operation requires a “carry out” if interpreted as an unsigned 32-bit integer (i.e. it requires 33 or more bits to represent)
movs r2, 0xFF000000
movs r3, 0xFF000000
adds r5, r2, r3
This status flag is set when the result of an ALU operation would overflow the min/max value if interpreted as a twos complement signed integer
movs r0, 0x7FFFFFFF @ largest signed integer
adds r0, 1
movs r0, 0x80000000 @ smallest signed integer
subs r0, 1
adc vs add
The adc (add with carry) instruction is really similar to the add instruction, but it also adds the current value of the carry flag to the result
mov r2, 16
adc r3, r1, r2
mov r2, 16
adc r3, r1, r2
What value will be in r3 a er the above instructions are executed?
Worked example: 64-bit addition
Can we add numbers bigger than the (32-bit) word size? Yes! assume numbers in r3 : r2 and r5 : r4
we want to store the 64-bit result in r1 : r0
adds r0, r2, r4 @ add least significant words, set flags
adcs r1, r3, r5 @ add most significant words and carry bit
More flags
The status register is 32-bit, and there are more flags than these 4—but theyʼre the main ones
Youʼll use them (a lot!) in the week 3 lab
Weʼll introduce the other flags as necessary later in the course
On purity…
Remember Haskell? Lovely pure functions—no outside state or side e ects The real world? Messy, stateful—yuck! But we can get things done
Arithmetic instructions
add{s} {
adc{s} {
add{s} {
adc{s} {
qadd {
sub{s} {
sbc{s} {
rsb{s} {
sub{s} {
sbc{s} {
rsb{s} {
qsub {
@ Rd := Rn – #
@ Rd := Rn – Rm @ sa
@ Rd := Rn + #
Questions?
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