5-Stage Pipeline Processor
● Lab 5 討論區
● Lab 5 is team work
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● Implement the datapath of 5-Stage Pipeline Processor as below
● You can refer to lab4 for additional details (mux, control signals, etc) ○ Appendix
Attached file
○ Lab5Code
● ALU_Ctrl.v
● Decoder.v
● Forwarding.v
● Hazard_detection.v
● Imm_Gen.v
● MUX_2to1, 3to1.v ● Shift_Left_1.v
● Pipeline_CPU.v
● IFID_register.v
● IDEXE_register.v
● EXEMEM_register.v ● MEMWB_register.v
● Validate the correction of your implementation
○ Please follow the readme.txt ( Lab5 need to run in UNIX-like operating system )
● Testcase
○ Lab5Answer/testcase_for_compile.txt 4
Pipeline register
● Pipeline stage
○ IF: Instruction fetch from memory
○ ID: Instruction decode & register read
○ EX: Execute operation or calculate address
○ MEM: Access memory operand
○ WB: Write result back to register
IF/ID pipeline register ID/EXE pipeline register
EXE/MEM pipeline register MEM/WB pipeline register
● To hold information produced in previous cycle
Pipeline register
Hint : (Clock Positive triggered)
clk_i) begin .
. // Code HERE
Forwarding unit
● Solving data dependency
○ Dependency detection and control
● You need to implement forwarding unit to follow the Data Forwarding Control Conditions
Hazard detection unit
● Solving Load-Use data hazard
● You need to implement Hazard detection unit to follow the condition
Branch Hazard
● Move branch decision from MEM to ID
● You also need to implement flush
NOP instruction
Case 1 : (Basic)
addi x1, x0,50 4 nop
addi x2, x0, 18 4 nop
sub x3, x1, x2 4 nop
add x4, x1, x3 4 nop
or x5, x1, x4 4 nop
and x6, x2, x4 4 nop
x1 = 50; x2 = 18; x3 = 32; x4 = 82; x5 = 114; x6 = 18;
● Lab5Answer/testcase_for_compile.txt
● In all case, initially
○ mem[16] = 2
○ All registers = 0
Case 8 : (medium)
addi x2,x2,6 addi x0,x0,0 slli x2,x2,1
result: x2 = 12
Case 11 : (Advanced)
lw x1,16(x2) add x3,x2,x1
x1 = 2,x3 = 2
● This script cannot run in Windows
● Put your .v file in Lab5Code
● $ chmod +x ./lab5TestScript.sh && ./lab5TestScript.sh
● Lab4 datapath
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