Integrated Electronics & Design
IC Fabrication Techniques II
Gary , PhD
https://www.xjtlu.edu.cn/en/departments/academic-departments/electrical-and-electronic-engineering/staff/chun-zhao
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IC Fab.Tech. OUTLINE
Thin Film Formation
Photolithography and Ecthing
IC Resistor
Sheet Resistance Diode
nMOSFET: Process Flow nMOSFET: Fab. and Layout nMOSFET: Layout Rules
EECS40, Fall 2004 Lecture 24a, Slide 2
Prof. White
IC Fabrication Techniques
• IC Resistor
• Sheet Resistance • Diode
EECS40, Fall 2004
Lecture 24a, Slide 3
Prof. White
Process Flow Example #1: Resistor
< 10mm x 1mm (10-7 cm2) Integrated R
~1cm x 1mm (10-1 cm-2)
Discrete R
EECS40, Fall 2004 Lecture 24a, Slide 4
Prof. White
Process Flow Example #1: Resistor
< 10mm x 1mm (10-7 cm2) Integrated R
~1cm x 1mm (10-1 cm-2)
Discrete R
EECS40, Fall 2004 Lecture 24a, Slide 5
Prof. White
Process Flow Example #1: Resistor
< 10mm x 1mm (10-7 cm2) Integrated R
~1cm x 1mm (10-1 cm-2)
EECS40, Fall 2004 Lecture 24a, Slide 6
Discrete R
Prof. White
Process Flow Example #1: Resistor
R L = L A tW
homogeneously doped sample
Lecture 7 Page 18
EECS40, Fall 2004 Lecture 24a, Slide 7
Prof. White
Process Flow Example #1: Resistor
Mask 3 for “metal”
Mask 1 for “body”
Mask 2 for “contact”
EECS40, Fall 2004 Lecture 24a, Slide 8
Prof. White
Process Flow Example #1: Resistor
negative resist
Oxide mask (dark field)
or Active mask
Contact mask (dark field)
Al mask (clear field)
positive resist
EECS40, Fall 2004 Lecture 24a, Slide 9
Prof. White
Process Flow Example #1: Resistor
Patterns transfer to wafer:
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
EECS40, Fall 2004 Lecture 24a,
Prof. White
Process Flow Example #1: Resistor
Three-mask process:
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: Step 2: Step 3:
Step 4: Step 5: Step 6: Step 7:
grow 500 nm of SiO2
pattern oxide using the oxide mask (dark field)
implant phosphorus and anneal to form an n-type
layer with ND = 1020 cm-3 and depth 100 nm
deposit oxide to a thickness of 500 nm
pattern deposited oxide using the contact mask (dark field) deposit aluminum to a thickness of 1 mm
pattern using the aluminum mask (clear field)
Layout: AA
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: oxidation, photolithography & etching
Oxidation & Photolithography - pattern resist
photoresist
Step 1: grow 500 nm of SiO2
photoresist patterned using mask #1
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: oxidation, photolithography & etching
Step 2: Pattern oxide
oxide etchant
photoresist patterned using mask #1
SiO2 + 6HF → H2SiF6+2H2O
Step 2: pattern oxide using the oxide mask (dark field)
photoresist patterned using mask #1
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: doping & annealing
Step 3: Implant & Anneal phosphorus implant:
Step 3: implant phosphorus and anneal to form an n-type layer with ND = 1020 cm-3 and depth 100 nm
phosphorus ions
phosphorus blocked by oxide
after anneal of phosphorus implant:
lateral diffusion of phosphorus under oxide during anneal
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: Metal contact
Step 4: Deposit 500 nm oxide
2nd layer of SiO2 1st layer of SiO2
Step 4: deposit oxide to a thickness of 500 nm Mask #2
Open holes for metal contacts
Step 5: Pattern oxide
Step 5: pattern deposited oxide using the contact mask (dark field)
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: Metal contact
Step 4: Deposit 500 nm oxide
2nd layer of SiO2 1st layer of SiO2
photoresist
Step 5: Pattern oxide
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: Metal contact
photoresist patterned using mask #2
Step 5: Pattern oxide
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: Metal contact
Step 5: Pattern oxide
oxide etchant
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: Metal contact
Step 5: Pattern oxide
Open holes for metal contacts
deposition, photolithography & etching
EECS40, Fall 2004 Lecture 24a,
Prof. White
Al deposition
A-A Cross-Section: metallization
deposition, photolithography & etching
Step 6: deposit aluminum to a thickness of 1 mm
Step 7: Pattern metal
Step 7: pattern using aluminum mask (clear field)
EECS40, Fall 2004 Lecture 24a,
Prof. White
After 7 steps
EECS40, Fall 2004 Lecture 24a,
Prof. White
Layer-to-Layer Alignment
Step 6: Mask #3 Al deposition
Step 7: Pattern metal
Open circuit
EECS40, Fall 2004 Lecture 24a,
Prof. White
Importance of Layer-to-Layer Alignment Example: metal line to contact hole
→ marginal contact
→ no contact!
safety margin to allow for misalignment
Example of Design Rule:
If the minimum feature size is 2l, then the safety margin for overlay error is l.
→Design Rules are needed:
• Interface between designer & process engineer • Guidelines for designing masks
EECS40, Fall 2004 Lecture 24a,
Prof. White
Registration of Each Mask
Registration of mask patterns is critical: show separate layouts to avoid ambiguity
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
“registration” shows overlay of patterns 0 scale in mm
1 for B-B “cut” 2
Registration of one mask to the next (also called “alignment” and
“overlay”) is a crucial aspect of lithography
EECS40, Fall 2004 Lecture 24a,
Prof. White
Same Layout but with registration (alignment)
perfect registration
0 scale in mm 1 for B-B “cut”
EECS40, Fall 2004 Lecture 24a,
Prof. White
Same Layout but with misregistration (misalignment) Metal mask
misaligned
0 scale in mm 1 for B-B “cut”
Open circuit
EECS40, Fall 2004 Lecture 24a,
Prof. White
Example of Design Rule: MOSIS • A minimum feature size is
Implementation System
Using 2l to stand for the minimum feature size the smallest dimension that can be produced.
2l = 32nm → 22nm 2l = 14nm
2l = 7nm → 5nm
Intel & IBM: SMIC:
EECS40, Fall 2004 Lecture 24a,
Prof. White
Example of Design Rule: MOSIS implementation
• If the minimum feature size is 2l, then the minimum active area width is 3l, the minimum metal width is 3l, and the safety margin for overlay error is l.
safety margin to allow for misalignment l
2l is the smallest dimension that can be produced.
the minimum active area width is 3l. For IC resistors, the width can be 2l.
the minimum metal width is 3l.
EECS40, Fall 2004 Lecture 24a,
Prof. White
EECS40, Fall 2004
MOSIS layout design rules
Lecture 24a,
Prof. White
EECS40, Fall 2004
MOSIS layout design rules
Lecture 24a,
Prof. White
IC Fabrication Techniques
• IC Resistor
• Sheet Resistance • Diode
EECS40, Fall 2004
Lecture 24a,
Prof. White
Using Sheet Resistance (Rs) • Ion-implanted (or “diffused”) IC resistor
What is the resistance??
EECS40, Fall 2004 Lecture 24a,
Prof. White
Electrical Resistance
homogeneously doped sample
R V = L = L = I A tW
(Unit: ohms)
Resistance
where is the resistivity (W•cm)
L t W
Sheet Resistivity (RS) Ω/sq or Sheet Resistance
EECS40, Fall 2004 Lecture 24a,
Prof. White
Using Sheet Resistance (Rs) • Ion-implanted (or “diffused”) IC resistor
EECS40, Fall 2004 Lecture 24a,
Prof. White
R = ρ L/A = (ρ/t) (L/W)
Sheet Resistivity (RS) Ω/sq or Sheet Resistance
R = Rs (L/W)
# of Squares
If L = W, R = RS
R = Rs (L/W)
R = 2RS R = RS/2 R = RS/3
EECS40, Fall 2004 Lecture 24a,
R = 8RS R ≈ 6.5RS
Prof. White
Using Sheet Resistance (Rs)
R=L=R L9R t W S W S
EECS40, Fall 2004 Lecture 24a,
Prof. White
Integrated-Circuit Resistors
The resistivity and thickness t are fixed for each layer in a given manufacturing process
A circuit designer specifies the length L and width W, to achieve a desired resistance R
R=RL s W
fixed designable
Example: Suppose we want to design a 5 kW resistor using
a layer of material with Rs = 200 W/ Resistor layout (top view)
Space-efficient layout
EECS40, Fall 2004 Lecture 24a,
Prof. White
IC Fabrication Techniques
• IC Resistor
• Sheet Resistance • Diode
EECS40, Fall 2004
Lecture 24a,
Prof. White
Process Flow Example #1: Resistor
EECS40, Fall 2004 Lecture 24a,
Prof. White
Process Flow Example #2: diode A -- A
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
EECS40, Fall 2004 Lecture 24a,
Prof. White
Process Flow Example #1: Diode
Three-mask process:
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: Step 2: Step 3:
Step 4: Step 5: Step 6: Step 7:
grow 500 nm of SiO2
pattern oxide using the oxide mask (dark field)
implant phosphorus and anneal to form an n-type
layer with ND = 1020 cm-3 and depth 100 nm
deposit oxide to a thickness of 500 nm
pattern deposited oxide using the contact mask (dark field) deposit aluminum to a thickness of 1 mm
pattern using the aluminum mask (clear field)
Layout: AA
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: oxidation, photolithography & etching
Step 1: Grow oxide
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: oxidation, photolithography & etching
oxide etchant
photoresist patterned using mask #1
Pattern oxide (active mask)
photoresist patterned using mask #1
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: doping & annealing
Step 3: Implant & Anneal
phosphorus implant:
phosphorus ions
phosphorus blocked by oxide
after anneal of phosphorus implant:
lateral diffusion of phosphorus under oxide during anneal
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: Metal contact
Step 4: Deposit 500 nm oxide
2nd layer of SiO2 1st layer of SiO2
Open holes for metal contacts
Pattern oxide (contact mask)
deposition, photolithography & etching
EECS40, Fall 2004 Lecture 24a,
Prof. White
A-A Cross-Section: metallization
deposition, photolithography & etching
Al deposition
Pattern metal (Metal mask)
EECS40, Fall 2004 Lecture 24a,
Prof. White
Example of Design Rule: MOSIS
• R1: the minimum feature size is 2l,
• R2: the minimum active area width is 3l,
• R3: the minimum metal width is 3l,
• R4: the safety margin for overlay error is l,
• R5: the minimum active contact spacing on different active regions is 6l.
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
EECS40, Fall 2004 Lecture 24a,
Prof. White
IC Fabrication Techniques
: Process Flow
: Layout Rule
Process Flow: nMOSFET
Mask 1: Active region
Process Flow: nMOSFET
• The cleaned Si slice is oxidized (oxide1)
• A window is opened
in the oxide (mask1).
• The sides of the mask
1 must be equal in size to a multiple of the minimum feature size (design rules).
Mask 1: Active region
Process Flow: nMOSFET
Mask 2: Gate
Process Flow: nMOSFET
Keep gate oxide
Oxide and polysilicon are photoengraved in the shape • of the gate stripe after mask (mask2) for the etching of polysilicon gate electrode.
The slice of silicon is re- oxidized (oxide2).
It fills the window with new thinner oxide. polysilicon covers the entire surface.
Process Flow: nMOSFET
• The oxide is etched from the source and drain regions.
• The implant creates the source and drain regions and dopes the polysilicon to make it very conducting.
Process Flow: nMOSFET
Mask 3: contacts
Each of these holes must have dimensions that are
Oxide is deposited on the surface (oxide 3)
The contact or via holes are opened (mask 3).
equal to the minimum feature size.
Process Flow: nMOSFET
Mask 4: metal
Mask 4: metal
Process Flow: nMOSFET
• Al is evaporated to cover the whole slice and is then covered with photoresist.
• Al is patterned into the shape of the conductor patterns across the chip (mask 4). It makes contact to the source and drain down the contact holes.
• The width of the Al stripes must cover the contact holes with an allowance on either side of an amount equal to the minimum alignment accuracy.
IC Fabrication Techniques
: Process Flow
: Layout Rule
Layout rules to minimise MOST size
4l Channel width
Channel length
2l of poly over active
the minimum gate extension
MOSIS layout design rules
Layout rules to minimise MOST size
minimum metal
minimum active contact to
1l metal edge spacing
4l (min. is 3l) spacing
minimum metal
The Design of a MOSFET
Example: if we need a MOSFET with W/L = 12, design its layout.
The Design of a MOSFET
Example: if we need a MOSFET with W/L = 0.5, design its layout.
Mask Sequence for a Polysilicon-Gate Transistor
mask1 mask2
Mask Sequence for a Polysilicon-Gate Transistor
mask1 mask2
Mask Sequence for a Polysilicon-Gate Transistor
⚫ Mask 1: Defines active area or thin oxide region of
transistor
⚫ Mask 2: Defines polysilicon
gate of transistor, mask 1
⚫ Mask 3: Delineates the
contact window, mask 2 & 1.
⚫ Mask 4: Delineates the metal
Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 2
aligns to mask 3.
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