Atmel | SMART ARM-based Embedded MPU DATASHEET
Description
The Atmel® | SMART SAM9261 is a complete system-on-chip built around the ARM926EJ-STM ARM® Thumb® processor with an extended DSP instruction set and Jazelle® Java® accelerator. It achieves 210 MIPS at 190 MHz.
The SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash.
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The SAM9261 integrates a ROM-based bootloader supporting code shadowing from, for example, external DataFlash® into external SDRAM. The software controlled Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency.
The SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints.
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
ARM926EJ-S ARM ThumbProcessor
̶ ̶ ̶ ̶ ̶ ̶ ̶
DSP Instruction Extensions
ARM Jazelle Technology for Java Acceleration
16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer 210 MIPS at 190 MHz
Memory Management Unit
EmbeddedICETM, Debug Communication Channel Support Mid-level implementation Embedded Trace Macrocell® (ETM®)
Additional Embedded Memories
̶ 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
̶ 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed
External Bus Interface (EBI)
̶ Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
LCD Controller
Supports Passive or Active Displays
Up to 16 bits per Pixel in STN Color Mode
Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048
USB 2.0 Full Speed (12 Mbits per second)
̶ Host Double Port: Dual On-chip Transceivers, Integrated FIFOs and Dedicated DMA Channels ̶ Device Port: On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs
Bus Matrix
Handles Five Masters and Five Slaves Boot Mode Select Option
Remap Command
Fully Featured System Controller (SYSC) for Efficient System Management, including
Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller
Advanced Interrupt Controller and Debug Unit
Periodic Interval Timer, Watchdog Timer and Real-time Timer
̶ Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC)
̶ Programmable Shutdown Pin Control and Wakeup Circuitry
Clock Generator (CKGR)
̶ 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock ̶ 3 to 20 MHz On-chip Oscillator and two PLLs
Power Management Controller (PMC)
̶ Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities ̶ Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
̶ Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
̶ Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Three 32-bit PIO Controllers Reset Controller (RSTC)
Debug Unit (DBGU)
̶ 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention ̶ Mode for General Purpose Two-wire UART Serial Communication
Periodic Interval Timer (PIT)
̶ 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
̶ Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
Real-Time Timer (RTT)
̶ 32-bit Free-running Backup Counter Running at Slow Clock
Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line
Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
Nineteen Peripheral DMA (PDC) Channels Multimedia Card Interface (MCI)
̶ SDCard and MultiMediaCardTM Compliant
̶ Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant Three Synchronous Serial Controllers (SSC)
Independent Clock and Frame Sync Signals for Each Receiver and Transmitter I2S Analog Interface Support, Time Division Multiplex Support
High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
̶ Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
̶ Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interface (SPI)
̶ 8 to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
One Three-channel 16-bit Timer/Counters (TC)
̶ Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
̶ Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two-wire Interface (TWI)
̶ Master Mode Support, All Two-wire Atmel EEPROMs Supported
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
̶ LFBGA217, 217-ball LFBGA, 15 x 15 mm, pitch 0.8mm
SAM9261 [DATASHEET] 3 Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Block Diagram
Figure 1-1. SAM9261 Block Diagram
System Controller
JTAG Boundary Scan
ARM926EJ-S Core
Fast ROM 32 Kbytes
5-layer Matrix
Peripheral Bridge
Peripheral DMA Controller
IOA PIOB PIOC
USB Device
SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
JTAGSEL TDI TDO TMS TCK NTRST RTCK
TST FIQ IRQ0–IRQ2 DRXD DTXD PCK0–PCK3
PLLRCA PLLRCB
XIN32 XOUT32
VDDBU GNDBU
VDDCORE NRST
MCCK MCCDA MCDA0–MCDA3
RXD0 TXD0 SCK0 RTS0 CTS0
RXD1 TXD1 SCK1 RTS1 CTS1
RXD2 TXD2 SCK2 RTS2 CTS2
SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3
SPI0_MISO SPI0_MOSI SPI0_SPCK
SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK
Timer Counter
TSYNC TCLK TPS0–TPS2 TPK0–TPK15
D0–D15 A0/NBS0 A1/NBS2/NWR2 A2–A15/A18–A21 A22/REG A16/BA0 A17/BA1
NCS2 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK
A23–A24 A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1
CFCE2 NCS6/NANDOE NCS7/NANDWE D16–D31
LCDD0–LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC
TF0 TK0 TD0 RD0 RK0 RF0
TF1 TK1 TD1 RD1 RK1 RF1
TF2 TK2 TD2 RD2 RK2 RF2
TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2
Instruction Cache MMU Data Cache 16 Kbytes 16 Kbytes
TCM Interface
Fast SRAM 160 Kbytes
CompactFlash NAND Flash
3–20 MHz Main Osc.
SDRAM Controller
Static Memory Controller
32 kHz XTAL Osc.
GPBR (16 bytes)
Transceiver Transceiver
Backup Section
2. Signal Description
Table 2-1. Signal Description by Peripheral
Signal Name Function Type Active Level Comments
EBI I/O Lines Power Supply
1.65–1.95 V and 3.0–3.6 V
Peripherals I/O Lines Power Supply
Backup I/O Lines Power Supply
1.08–1.32 V
PLL Power Supply
Oscillator Power Supply
Core Chip Power Supply
1.08–1.32 V
PLL Ground
Oscillator Ground
Backup Ground
Clocks, Oscillators and PLLs
Main Oscillator Input
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
PLL Filter
PLL Filter
Programmable Clock Output
Shutdown, Wakeup Logic
SHDN Shutdown Control Output Do not tie over VDDBU
WKUP Wakeup Input Input Accepts between 0V and VDDBU
ICE and JTAG
Test Clock
No pull-up resistor
Returned Test Clock
No pull-up resistor
Test Data In
No pull-up resistor
Test Data Out
Test Mode Select
No pull-up resistor
Test Reset Signal
Pull-up resistor
JTAG Selection
Pull-down resistor. Accepts between 0V and VDDBU.
Embedded Trace Macrocell – ETM
Trace Synchronization Signal
Trace Clock
Trace ARM Pipeline Status
TPK0–TPK15
Trace Packet Port
SAM9261 [DATASHEET] 5 Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Table 2-1. Signal Description by Peripheral (Continued)
Signal Name Function Type Active Level Comments
Reset/Test
Microcontroller Reset
Pull-up resistor
Test Mode Select
Pull-down resistor
Boot Mode Select
Debug Unit – DBGU
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
Advanced Interrupt Controller – AIC
IRQ0–IRQ2 External Interrupt Inputs Input
FIQ Fast Interrupt Input Input
PIO Controller – PIOA / PIOB / PIOC
Parallel IO Controller A
Pulled up input at reset
Parallel IO Controller B
Pulled up input at reset
Parallel IO Controller C
Pulled up input at reset
External Bus Interface – EBI
Pulled up input at reset
Address Bus
0 at reset
External Wait Signal
Static Memory Controller – SMC
Chip Select Lines
Write Signal
Read Signal
Write Enable
Byte Mask Signal
CompactFlash Support
CFCE1–CFCE2
CompactFlash Chip Enable
CompactFlash Output Enable
CompactFlash Write Enable
CompactFlash IO Read
CompactFlash IO Write
CompactFlash Read Not Write
CFCS0–CFCS1
CompactFlash Chip Select Lines
NAND Flash Support
NAND Flash Output Enable
NAND Flash Write Enable
NAND Flash Chip Select
6 SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Table 2-1. Signal Description by Peripheral (Continued)
Signal Name Function Type Active Level Comments
SDRAM Controller – SDRAMC
SDRAM Clock
SDRAM Clock Enable
SDRAM Controller Chip Select
Bank Select
SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Multimedia Card Interface – MCI
Multimedia Card Clock
Multimedia Card A Command
MCDA0–MCDA3
Multimedia Card A Data
Universal Synchronous Asynchronous Receiver Transmitter – USART
Serial Clock
Transmit Data
Receive Data
Request To Send
Clear To Send
Synchronous Serial Controller – SSC
Transmit Data
Receive Data
Transmit Clock
Receive Clock
Transmit Frame Sync
Receive Frame Sync
Timer/Counter – TC
TCLK0–TCLK2
External Clock Input
TIOA0–TIOA2
I/O Line A
TIOB0–TIOB2
I/O Line B
Serial Peripheral Interface – SPI
SPI0_MISO, SPI1_MISO
Master In Slave Out
SPI0_MOSI, SPI1_MOSI
Master Out Slave In
SPI0_SPCK, SPI1_SPCK
SPI Serial Clock
SPI0_NPCS0, SPI1_NPCS0
SPI Peripheral Chip Select 0
SPI0_NPCS1–SPI0_NPCS3, SPI1_NPCS1–SPI1_NPCS3
SPI Peripheral Chip Select
SAM9261 [DATASHEET] 7 Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Table 2-1. Signal Description by Peripheral (Continued)
Signal Name Function Type Active Level Comments
Two-Wire Interface – TWI
TWD Two-wire Serial Data I/O
TWCK Two-wire Serial Clock I/O
LCD Controller – LCDC
LCDD0–LCDD23
LCD Data Bus
LCD Vertical Synchronization
LCD Horizontal Synchronization
LCD Dot Clock
LCD Data Enable
LCD Contrast Control
USB Device Port – UDP
DDM USB Device Port Data – Analog
DDP USB Device Port Data + Analog
USB Host Port – UHP
USB Host Port A Data –
USB Host Port A Data +
USB Host Port B Data –
USB Host Port B Data +
8 SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
3. Package and Pinout
3.1 217-ball LFBGA Package Outline
Figure 3-1 shows the orientation of the 217-ball LFBGA package.
A detailed mechanical description is given in Section 39. “Mechanical Characteristics”.
Figure 3-1. 217-ball LFBGA Package Outline (Top View)
3.2 Pinout
Table 3-1. SAM9261 Pinout for 217-ball LFBGA Package Pin(1) Pin(1)
Pin(1) Pin(1)
Signal Name
Signal Name
NWR1/NBS1/CFIOR
NWR0/NWE/CFWE
NWR3/NBS3/CFIOW
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ABCDEFGHJKLMNPRTU
Signal Name
PA31 T4 PC2
Signal Name
SAM9261 [DATASHEET] 9 Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Table 3-1. SAM9261 Pinout for 217-ball LFBGA Package (Continued)
Pin(1) Pin(1)
Pin(1) Pin(1)
Signal Name
A1/NBS2/NWR2
Signal Name
Signal Name
NCS3/NANDCS
Note: 1. Shaded cells define the pins powered by VDDIOM. 2. NC pins must be left unconnected.
10 SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Signal Name
4. Power Considerations 4.1 Power Supplies
The SAM9261 device has several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have separate grounds. See Table 4-1.
Table 4-1. SAM9263 Power Supply Pins
Item(s) powered
Core, including the processor Embedded memories Peripherals
1.08–1.32 V
External Bus Interface I/O lines
1.65–1.95 V(1)
3.0–3.6 V(1)
Peripheral I/O lines USB transceivers
Main oscillator cells
Slow Clock oscillator
Part of the System Controller
1.08–1.32 V
Note: 1. Desired voltage range selectable by software
The double power supplies VDDIOM and VDDIOP are identified in Table 3-1 on page 9. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals.
4.2 Power Sequence Requirements
The SAM9261 board design must comply with the guidelines described in Section 4.2.1 “Powerup Sequence” and Section 4.2.2 “Powerdown Sequence” to guarantee reliable operation of the device. Any deviation from these sequences may prevent the device from booting.
SAM9261 [DATASHEET] 11 Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Powerup Sequence
Figure 4-1. VDDCORE and VDDIO Constraints at Startup
VDDIO > Voh
VDDIO > Vih
Powerdown Sequence
Switch off the VDDIOM and VDDIOP power supply prior to or at the same time as VDDCORE. No powerup or powerdown restrictions apply to other power supplies.
SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
VDDCOREtyp
Core Supply POR Output
<--- tRST ---> < T1 ><------------ T2----------->
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their target values prior to the release of POR.
VDDIOP must be ≥ to VIH (refer to Table 38-2 “DC Characteristics” for more details) within (tRST + T1) after VDDCORE has reached VT+.
VDDIOM must reach VOH (refer to Table 38-2 “DC Characteristics” for more details) within (tRST + T1 + T2) after VDDCORE has reached VT+.
tRST=50μs T1=91.5μs T2=488μs
tRST is a POR characteristic T1 = 3 x tSLCK
T2 = 16 x tSLCK
As tSLCK is the period of the external 32.768 kHz oscillator.
5. I/O Line Considerations
5.1 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.
The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low level. It integrates a permanent pull-up resistor of about 15 kΩ to VDDIOP, so that it can be left unconnected for normal operations.
5.2 Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results.
5.3 Reset Pin
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can be left unconnected in case no reset from the system needs to be applied to the product.
The NRST pin integrates a permanent pull-up resistor of 100 kΩ minimum to VDDIOP. The NRST signal is inserted in the Boundar
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