DESN2000: Engineering Design & Professional Practice (EE&T)
Week 7 Procedural call standard Input and output interfaces
School of Electrical Engineering & Telecommunications Graduate School of Biomedical Engineering
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Biomedical Microsystems Lab
• Function call examples
• Input / output background
• Interrupts
• LPC2478 microcontroller
© 2022 UNSW Sydney
Revision: AAPCS
• Caller’s rights:
1. Use V1 – V8 freely.
2. Assume that the return values are placed in A1 – A4 by the callee.
• Callee’s rights:
1. Use A1 – A4 freely.
2. Assume that the arguments are available in A1 – A4 (additional arguments are on stack).
© 2022 UNSW Sydney
Revision: AAPCS
• Caller’s responsibility:
Save LR before BL.
Save A1 – A4 if these registers are used for any operations after BL to callee.
Because callee might modify them.
Place first 4 arguments in A1 – A4. Use stack if more than 4 arguments, e.g.: 5th at [SP, #0]
6th at [SP, #4]
• Callee’s responsibilities
1. Save V1 – V8 before using them and restore the original values before returning.
2. If not void, place return values in A1 – A4.
3. Return to caller by performing MOV PC, LR.
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Summary of stack frame
Func1() called Func2(), processor is executing Func2(). Stack frame might look like the following, in the most general case:
Main memory
Func1() Callee save reg (V1 – V8)
Needed if using any of V1 – V8
If 8 registers aren’t enough, swap to/from mem
Might need if calling another function (passing arg(s) and/or getting return value)
Needed if calling another function
Might need if callee takes > 4 integer arguments
Stack frame
Temporaries Caller save reg (A1 – A4) Link reg (LR)
Extra arguments (≥ 5th)
Callee save reg (V1 – V8) Temporaries
Caller save reg (A1 – A4)
Func2() Stack frame
Stack pointer advances with function call, rewinds when returning.
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Assembly example
• Build a recursive function to compute the nth Fibonacci Number.
• The Fibonacci numbers F⇢(n) are defined as
F(n) = • Implementation in C
int fib(int n) { if (n == 0)
return 1; if (n == 1)
F(n 1) + F(n 2)
if n = 0, 1 otherwise
return fib(n-1) + fib(n-2);
• A recursive function – calls itself repeatedly until leaf conditions (n = 0, n = 1) are reached.
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Assembly example
• How does the recursion work?
F(3) = F(2) + F(1)
= F(1) + F(0) + 1 =1+1+1=3
BL fib (1)
BL fib (0)
xxxx MOV PC, LR
xxxx MOV PC, LR
BL fib (2)
BL fib (1)
xxxx MOV PC, LR
xxxx MOV PC, LR
xxxx MOV PC, LR
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Assembly example
• Being AAPCS-compliant is critical for recursive functions, to avoid resource conflicts with nested function calls.
• Step 1: Identify registers to be saved and frame size.
• Save LR, because F(n) calls F(n-1) and F(n-2).
• Save V1 for intermediate result computation.
• Save A1 to pass argument to F(n-1) and F(n-2), and to return result.
• Therefore a stack frame of 3 words.
• So assembly code must have:
STR LR, [SP, #-4]! STR V1, [SP, #-4]! …
STR A1, [SP, #-4]!
• Identically:
STMFD SP!, { A1, V1, LR }
NOTE: this line appears in function body
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Assembly example
Step 2.1: Implement the function body
• Starting with the leaf cases • Assembly:
fib_body CMP A1, #0 CMPNE A1, #1 MOVEQ A1, #1
BEQ fib_fin
Step 2.2: Implement the function body
• The recursive part • Assembly:
STR A1, [SP, #-4]! SUB A1,A1,#1
MOV V1, A1
LDR A1, [SP], #4 SUB A1,A1,#2 BL fib
ADD A1, A1, V1
F(n 1) + F(n 2)
ifn=0,1 otherwise
; if (n==0)
; if (n==1)
; return 1
; need A1 after BL ;A1=n-1
; save ret value ; restore A1 ;A1=n-2
; fib(n-2)
; A1 = fib(n-1) + fib(n-2)
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Assembly example
Step 3: Returning
Removing stack frame. Placing return value in A1. Adjust PC, leaving fib().
So assembly code must have:
NOTE: this line appears in function body
LDMFD SP!, { A1, V1, LR }
LDR A1, [SP], #4 …
LDR V1, [SP], #4 LDR LR, [SP], #4 MOV PC, LR
Identically:
; restore A1
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Assembly example
The complete assembly program
Function name
STR LR, [SP, #-4]! STR V1, [SP, #-4]!
CMP A1, #0 CMPNE A1, #1 MOVEQ A1, #1 BEQ fib_fin
STR A1, [SP, #-4]! SUB A1,A1,#1
MOV V1, A1
Function call housekeeping
; if (n==0) ; if (n==1)
; return 1
; need A1 after BL
;A1=n-1 Work
; save ret value ; restore A1 ;A1=n-2
; fib(n-2)
; A1 = fib(n-1) + fib(n-2)
Function call housekeeping
LDR A1, [SP], #4 SUB A1,A1,#2 BL fib
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Input / output background
• Why I/O devices?
• Human interacting with computers.
• Computer interacting with environment.
I/O devices Input
Input+output Disk
Keyboard Mouse
Display Printer
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Input / output examples
• I/O speed: bytes transferred per second.
• Wide range of data rates:
Behaviour Partner Data rate (kB/s)
Input Human 0.01
Laser printer Network-LAN
Input Output I or O
Human 0.02 Human 100 Machine 1,000,000
Line printer
Output Human 1
Magnetic disk
Storage Machine 100,000
Graphics display
Output Human 8,000,000
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What’s required to make I/O work?
connect many device types to the processor and memory. control these devices, respond to them, and transfer data. present these devices to user programs.
For embedded microprocessors (e.g. ARM):
status/cmd reg.
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Buses in Intel x86 PC
Use bus hierarchy – reduces latency.
Fastest ones closest to the CPU, slow ones are physically distant. Similar devices clustered on the same bus.
Backside bus
Frontside bus
Several 100 MHz
Graphics card
PCI-E devices
ISA devices
ISAbus 8MHz
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L2/L3 cache
AGP chipset
Mem controller
North bridge
South bridge
Accessing devices from CPU
• Model 1: dedicated I/O instructions.
• Model 2: memory mapped I/O (used by ARM):
• A portion of the address space is dedicated to I/O paths.
• Input: read a sequence of bytes
• Output: write a sequence of bytes
controller
Dev controller
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Memory mapped I/O
• I/O devices have registers for • Status / control
• These registers have interfaces similar to memory and can be connected to the memory
Memory Mapped I/O
• Reading / writing “special” memory locations produces the desired change(s) in the I/O
I/O devices often have a few registers
device controller.
– Status/ Control registers
• Typically, devices map to only a few bytes in memory.
– Data registers
These registers have interfaces that are similar to memory and can be connected to the memory bus
‒ Reads/Writes to certain locations will produce the desired change in the I/O device controller
0x10000000
0x100000C0 0xFFFFFFFF
g. data reg.
g. data reg.
Typically, devices map to
only a few bytes in
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Processor & I/O speed mismatch
• A 500 MHz microprocessor can execute 500 million load / store instructions per sec (2,000,000 kB/s data rate).
• I/O device might be 0.01 kB/s (e.g. keyboards).
• Input: device may not be ready to send data as fast as the processor loads it.
E.g. waiting for human inputs.
• Output: device may not be ready to accept data as fast as processor stores it.
• Need to address the big speed mismatch.
1. Polling I/O
2. Interrupt-driven I/O
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Accessing devices: polling
• Path to device generally has 2 registers:
• Status Register: says it’s OK to read/write (I/O ready).
• Data Register: data resides here.
• Polling procedure:
Read status reg No
Ready bit HI?
Read data reg Reset status reg
…by IO device
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Accessing devices: polling
• Polling can be expensive.
• Assuming a 500-MHz processor taking 400 clock cycles for a polling operation (calling poll routine, accessing the device and returning). Determine % of processor time for polling these devices:
1. Mouse: polled 30 times/sec so as not to miss user movement
2. Hard disk: transfers data in 16-byte chunks and can transfer at 8 MB/second. No transfer can be missed.
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Accessing devices: polling
• Polling clocks/sec = 400 clocks/sec × 30 = 12000 clocks/sec
• % of processor time for servicing device: 12×103 ÷ 500×106 = 0.002%
• Small impact to processor (indeed a common strategy).
• Hard disk
• Times polling disk/sec = 8 MB/s ÷ 16B = 500K polls/sec
• Polling clocks/sec = 400 clocks/sec × 500K = 200,000,000 clocks/sec
• % of processor time for servicing device: 200×106 ÷ 500×106 = 40%
• Unacceptable!
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Accessing devices: interrupt-driven
• Wasteful spending so much time spin-waiting for I/O.
• Solution: use an interrupt mechanism – notify CPU only when I/O is ready. Freeing up the CPU to do work in parallel.
Computation
I/O device busy
Service I/O
Computation
Computation
I/O device busy
Service I/O
Recv’ed interrupt
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Accessing devices: interrupt-driven
• Hard disk: transfers data in 16-byte chunks at 8 MB/second. No transfer can be missed
… as before
500 clock cycle overhead per transfer, including interrupt (100 more than before, for interrupt mech). Find the % of processor consumed if the hard disk is only active 5% of the time.
• When disk is active: interrupt rate = polling rate
• Disk interrupts / sec = 8 MB/s ÷ 16B = 500K interrupts/sec
• Disk Polling Clocks/sec = 500 × 500K = 250,000,000 clocks/sec
• % of processor time for servicing device during transfer: 250×106 ÷ 500×106 = 50%
• Average % of processor time for servicing device: disk active 5% of time, so 5% × 50% = 2.5%
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Memory-mapped IO on LPC2478
• Specific memory addresses correspond to registers, which are responsible for driving actual I/O pins on the microcontroller.
• Write to specific memory addresses to provide outputs
• Read specific memory addresses to get inputs.
• The ARM architecture use memory-mapped I/O.
© 2022 UNSW Sydney
NXP Semiconductors
Memory-mapped IO on LPC2478
5. Block diagram
16 kB SRAM
Single-chip 16-bit/32-bit microcontroller
XTAL1 XTAL2
system clock
TMS TDI TRST TCK TDO
trace signals
VDD(3V3) VDDA
• ARM7TDMI-S processor.
• 72 MHz clock.
• 512kB on-chip flash memory.
• 32-bit ARM and 16-bit Thumb instructions.
• 10/100 Ethernet controller.
• USB2 device controller.
P0, P1, P2, P3, P4
SRAM FLASH
EXTIN0 DBGEN PLL
VSSA, VSSIO, VSSCORE VDD(DCDC)(3V3)
D[31:0] A[23:0] control lines
port1 port2
8 × LCD control LCDVD[23:0] LCDCLKIN
3 × I2SRX 3 × I2STX
SCK0, SCK MOSI0, MOSI MISO0, MISO SSEL0, SSEL
SCK1 MOSI1 MISO1 SSEL1
MCICLK, MCIPWR
MCICMD, MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1, DTR1, RTS1 RXD1, DSR1, CTS1, DCD1, RI1
RD1, RD2 TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
16 kB SRAM
AHB BRIDGE
AHB BRIDGE
EINT3 to EINT0
2 × CAP0/CAP1/ CAP2/CAP3 4 × MAT2/MAT3, 2 × MAT0, 3×MAT1 6 × PWM0/PWM1
1 × PCAP0, 2 × PCAP1
8 × AD0 AOUT
HIGH-SPEED GPIO 160 PINS
ETHERNET MAC WITH DMA
INTERNAL CONTROLLERS
TEST/DEBUG INTERFACE
ARM7TDMI-S
MASTER AHB TO SLAVE PORT AHB BRIDGE PORT
SYSTEM FUNCTIONS
INTERNAL RC OSCILLATOR
SRAM FLASH
EXTERNAL MEMORY CONTROLLER
USB DEVICE/ HOST/OTG WITH
4 kB RAM AND DMA
AHB TO APB BRIDGE
GP DMA CONTROLLER
EXTERNAL INTERRUPTS
LCD INTERFACE WITH DMA
CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3
I2S INTERFACE
PWM0, PWM1
SSP0/SPI INTERFACE
LEGACY GPI/O 64 PINS TOTAL
A/D CONVERTER
SSP1 INTERFACE
D/A CONVERTER
SD/MMC CARD INTERFACE
power domain 2
RTCX1 RTCX2
2 kB BATTERY RAM
RTC OSCILLATOR
REAL- TIME CLOCK
UART0, UART2, UART3
CAN1, CAN2
WATCHDOG TIMER
SYSTEM CONTROL
I2C0, I2C1, I2C2
LPC2478 block diagram
© 2022 UNSW Sydney
Product data sheet
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Rev. 3.1 — 16 October 2013
EMULATION TRACE MODULE
NXP Semiconductors
Memory-mapped IO on LPC2478
5. Block diagram
16 kB SRAM
Single-chip 16-bit/32-bit microcontroller
XTAL1 XTAL2
system clock
TMS TDI TRST TCK TDO
trace signals
VDD(3V3) VDDA
• 2 CAN (controller area network) channels.
• 2 PWM units.
• 3 I2C interfaces.
• I2S (inter-IC sound) interface.
• 2 SSP (synchronous serial ports).
• SPI (serial peripheral interface) port.
P0, P1, P2, P3, P4
SRAM FLASH
EXTIN0 DBGEN PLL
VSSA, VSSIO, VSSCORE VDD(DCDC)(3V3)
D[31:0] A[23:0] control lines
port1 port2
8 × LCD control LCDVD[23:0] LCDCLKIN
3 × I2SRX 3 × I2STX
SCK0, SCK MOSI0, MOSI MISO0, MISO SSEL0, SSEL
SCK1 MOSI1 MISO1 SSEL1
MCICLK, MCIPWR
MCICMD, MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1, DTR1, RTS1 RXD1, DSR1, CTS1, DCD1, RI1
RD1, RD2 TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
16 kB SRAM
AHB BRIDGE
AHB BRIDGE
EINT3 to EINT0
2 × CAP0/CAP1/ CAP2/CAP3 4 × MAT2/MAT3, 2 × MAT0, 3×MAT1 6 × PWM0/PWM1
1 × PCAP0, 2 × PCAP1
8 × AD0 AOUT
HIGH-SPEED GPIO 160 PINS
ETHERNET MAC WITH DMA
INTERNAL CONTROLLERS
TEST/DEBUG INTERFACE
ARM7TDMI-S
MASTER AHB TO SLAVE PORT AHB BRIDGE PORT
SYSTEM FUNCTIONS
INTERNAL RC OSCILLATOR
SRAM FLASH
EXTERNAL MEMORY CONTROLLER
USB DEVICE/ HOST/OTG WITH
4 kB RAM AND DMA
AHB TO APB BRIDGE
GP DMA CONTROLLER
EXTERNAL INTERRUPTS
LCD INTERFACE WITH DMA
CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3
I2S INTERFACE
PWM0, PWM1
SSP0/SPI INTERFACE
LEGACY GPI/O 64 PINS TOTAL
A/D CONVERTER
SSP1 INTERFACE
D/A CONVERTER
SD/MMC CARD INTERFACE
power domain 2
RTCX1 RTCX2
2 kB BATTERY RAM
RTC OSCILLATOR
REAL- TIME CLOCK
UART0, UART2, UART3
CAN1, CAN2
WATCHDOG TIMER
SYSTEM CONTROL
I2C0, I2C1, I2C2
LPC2478 block diagram
© 2022 UNSW Sydney
Product data sheet
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Rev. 3.1 — 16 October 2013
EMULATION TRACE MODULE
NXP Semiconductors
Memory-mapped IO on LPC2478
5. Block diagram
16 kB SRAM
Single-chip 16-bit/32-bit microcontroller
XTAL1 XTAL2
system clock
TMS TDI TRST TCK TDO
trace signals
VDD(3V3) VDDA
• 160 high-speed GPIO (general purpose IO) pins.
• 64 legacy GPIO pins.
• 4 UART (universal asynchronous receiver-transmitter).
• 10-bit D/A converter.
• 10-bit A/D converter.
• 4 timers.
• LCD interface.
P0, P1, P2, P3, P4
SRAM FLASH
EXTIN0 DBGEN PLL
VSSA, VSSIO, VSSCORE VDD(DCDC)(3V3)
D[31:0] A[23:0] control lines
port1 port2
8 × LCD control LCDVD[23:0] LCDCLKIN
3 × I2SRX 3 × I2STX
SCK0, SCK MOSI0, MOSI MISO0, MISO SSEL0, SSEL
SCK1 MOSI1 MISO1 SSEL1
MCICLK, MCIPWR
MCICMD, MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1, DTR1, RTS1 RXD1, DSR1, CTS1, DCD1, RI1
RD1, RD2 TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
16 kB SRAM
AHB BRIDGE
AHB BRIDGE
EINT3 to EINT0
2 × CAP0/CAP1/ CAP2/CAP3 4 × MAT2/MAT3, 2 × MAT0, 3×MAT1 6 × PWM0/PWM1
1 × PCAP0, 2 × PCAP1
8 × AD0 AOUT
HIGH-SPEED GPIO 160 PINS
ETHERNET MAC WITH DMA
INTERNAL CONTROLLERS
TEST/DEBUG INTERFACE
ARM7TDMI-S
MASTER AHB TO SLAVE PORT AHB BRIDGE PORT
SYSTEM FUNCTIONS
INTERNAL RC OSCILLATOR
SRAM FLASH
EXTERNAL MEMORY CONTROLLER
USB DEVICE/ HOST/OTG WITH
4 kB RAM AND DMA
AHB TO APB BRIDGE
GP DMA CONTROLLER
EXTERNAL INTERRUPTS
LCD INTERFACE WITH DMA
CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3
I2S INTERFACE
PWM0, PWM1
SSP0/SPI INTERFACE
LEGACY GPI/O 64 PINS TOTAL
A/D CONVERTER
SSP1 INTERFACE
D/A CONVERTER
SD/MMC CARD INTERFACE
power domain 2
RTCX1 RTCX2
2 kB BATTERY RAM
RTC OSCILLATOR
REAL- TIME CLOCK
UART0, UART2, UART3
CAN1, CAN2
WATCHDOG TIMER
SYSTEM CONTROL
I2C0, I2C1, I2C2
LPC2478 block diagram
© 2022 UNSW Sydney
Product data sheet
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Rev. 3.1 — 16 October 2013
EMULATION TRACE MODULE
Four dynamic memory banks, 256 MB each
Memory-mapped IO on LPC2478
0xE000 0000 to APB Peripherals 36 peripheral blocks, 16 kB each 0xEFFF FFFF
0xF000 0000 to AHB peripherals 0xFFFF FFFF
Table 16. LPC2468/78 memory usage and details
0xA000 0000 – 0xAFFF FFFF Dynamic memory bank 0
0xB000 0000 – 0xBFFF FFFF Dynamic memory bank 1
0xC000 0000 – 0xCFFF FFFF Dynamic memory bank 2
0xD000 0000 – 0xDFFF FFFF Dynamic memory bank 3
Address range General use
Address range details and description
0x0000 0000 to 0x3FFF FFFF
0x4000 0000 to 0x7FFF FFFF
0x8000 0000 to 0xDFFF FFFF
On-chip non-volatile memory and Fast I/O
On-chip RAM
Off-Chip Memory
0x0000 0000 – 0x0007 FFFF 0x3FFF C000 – 0x3FFF FFFF 0x4000 0000 – 0x4000 FFFF 0x7FE0 0000 – 0x7FE0 3FFF 0x7FD0 0000 – 0x7FD0 3FFF Four static memory banks, 16 0x8000 0000 – 0x80FF FFFF 0x8100 0000 – 0x81FF FFFF 0x8200 0000 – 0x82FF FFFF 0x8300 0000 – 0x83FF FFFF Four dynamic memory banks, 0xA000 0000 – 0xAFFF FFFF 0xB000 0000 – 0xBFFF FFFF 0xC000 0000 – 0xCFFF FFFF 0xD000 0000 – 0xDFFF FFFF 36 peripheral blocks, 16 kB each
Flash Memory (512 kB) Fast GPIO registers RAM (64 kB)
Ethernet RAM (16 kB) USB RAM (16 kB)
0xE000 0000 to 0xEFFF FFFF
0xF000 0000 to 0xFFFF FFFF
APB Peripherals AHB peripherals
Static memory bank 0
Static memory bank 1 Static memory bank 2 Static memory bank 3
256 MB each
Dynamic memory bank 0
Dynamic memory bank 1 Dynamic memory bank 2 Dynamic memory bank 3
© NXP B.V. 2009. All rights reserved.
ULMP10C2372_4XX User manual. Document No: UM10237
User manual Rev. 04 — 26 August 2009
© 2022 UNSW Sydney
The LPC2400 incorporates several distinct memory regions, shown in the following
UM10237 Chapter 2: LPC24XX Memory mapping
0xFFFF FFFF
0xFFE0 0000 0xFFDF FFFF
figures. Figure 2–6 shows the overall map of the entire address space from the user Memory-mapped IO on LPC2478
program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.
4.0 GB 3.75 GB
0xFFFF FFFF 0xF000 0000
0xE000 0000
4.0 GB – 2 MB
NXP Semiconductors
AHB PERIPHERALS
APB PERIPHERALS
AHB PERIPHERALS
APB PERIPHERALS
EXTERNAL STATIC AND DYNAMIC MEMORY
BOOT ROM AND BOOT FLASH
RESERVED ADDRESS SPACE
ON-CHIP STATIC RAM
SPECIAL REGISTERS
RESERVED ADDRESS SPACE
ON-CHIP NON-VOLATILE MEMORY OR RESERVED
0x8000 0000 0x7FFF FFFF
0x4000 0000 0x3FFF FFFF
0x3FFF 8000
0x0000 0000
LPC2400 system memory map
3.5 GB + 2 MB
Peripheral memory map
0xE020 0000 0xE01F FFFF
0xE000 0000
0xF000 0000 0xEFFF FFFF
© 2022 UNSW Sydney
Figure 8 and Table 2–17 show different views of the peripheral address space. Both the
AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
Semiconductors UM10237
anual Rev. 04 — 26 August 2009 20 of 792 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of
UM10237 Chapter 2: LPC24XX Memory mapping
0xFFFF FFFF
0xFFE0 0000 0xFFDF FFFF
their size. This eliminates the need for byte lane mapping hardware that
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