Lecture 01 Introduction to Programming in C 2 Eric Chen 2019-03-05 Objectives –Introduction • Motivation to learn C • Understand what a computer is and what a program is • the von Neumann model and programming • C program development process • CodeBlocks programming enviornment Programming in C • How many computer languages do you […]
Computer Architecture ELEC3441 Lecture 5 – Pipelining Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering RISC vs CISC – Iron Law CPUTime = # of instruction × # of cycle × time program instruction cycle L4 L5,6 HKUEEE ENGG3441 – HS 2 Microarchitecture CPI Cycle Time CISC >1 short RISC – single cycle
Computer Architecture ELEC3441 Lecture 6 – Branch Prediction + Interrupts Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Why an Instruction may not be dispatched every cycle (CPI>1) § Full bypassing may be too expensive to implement – typically all frequently used paths are provided – some infrequently used bypass paths may increase
Computer Architecture ELEC3441 Lecture 8 – Cache Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering CPU-Memory Bottleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency n Latency (time for a single access) • Memory access time >> Processor cycle time n Bandwidth (number of accesses per unit
CS计算机代考程序代写 algorithm computer architecture RISC-V cache Computer Architecture ELEC3441 Read More »
Computer Architecture ELEC3441 Lecture 4 – Single Cycle Processor Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Overview n First implementation the RISC-V ISA in this course • Morevariationstocome… n Single cycle processor: • Eachinstructiontakes1cycletocomplete n Idealized memory • Instantaneousread • Singlecyclewrite n Implements base RV32 HKU EEE ENGG3441 – HS 2 Full
CS计算机代考程序代写 computer architecture RISC-V Computer Architecture ELEC3441 Read More »
Computer Architecture ELEC3441 Instruction Set Architecture (1) 2nd Semester, 2020-21 Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Review: ISA n Instruction set architecture defines the user observable behavior a processor • Acontractbetweenhardwareandsoftware n Usually includes: • Observablestateofaprocessor • Asetofmachineinstructions • Semanticsoftheinstructionandprocessor execution HKU EEE ELEC3441 – HS 2 Computer Architecture: HW/SW Interface
Computer Architecture ELEC3441 Lecture 10 – Virtual Memory Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Physical Address Physical Address Bare Machine PC Inst. Cache D Decode E + M Data Cache W Physical Address Physical Address Memory Controller Main Memory (DRAM) § In a bare machine, the only kind of address is
Computer Architecture ELEC3441 Lecture 9 – Cache (2) Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Causes of Cache Misses: The 3 C’s Compulsory: first reference to a line (a.k.a. cold start misses) – misses that would occur even with infinite cache Capacity: cache is too small to hold all data needed by
Computer Architecture ELEC3441 Computer Performance 2nd Semester, 2020-21 Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering University of Hong Kong How do you measure performance of a computer? How do you make a computer fast? HKU EEE ELEC3441 – HS 2 Ways to measure Performance Execution Time Throughput Time to finish a task
Computer Architecture ELEC3441 Lecture 11 – Advanced Pipeline Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Simple pipeline so far… n CPI of simple pipelined processor is always >= 1 • Commitsatmost1instructionpercycle n Stalling and wasted cycles increase CPI • Cachemiss • TLBmiss • pagefault • Branchmisprediction HKUEEE ENGG3441 – HS 2 Challenges